Struct Ssc0 

#[repr(transparent)]
pub struct Ssc0(pub u32);

TSI SSC Register 0

Tuple Fields

0: u32

Implementations

impl Ssc0

pub const fn ssc_prescale_num(&self) -> u16

Full 12-bit numeric divider: main_clock/(N+1). The listed powers of two are examples, not the complete legal range.

pub const fn set_ssc_prescale_num(&mut self, val: u16)

Full 12-bit numeric divider: main_clock/(N+1). The listed powers of two are examples, not the complete legal range.

pub const fn base_nocharge_num(&self) -> u8

BASE_NOCHARGE_NUM. Encodings: 0: The SSC output bit 1’s basic period will be 1 clock cycle of system clock; 1: The SSC output bit 1’s basic period will be 2 clock cycles of system clock; 2: The SSC output bit 1’s basic period will be 3 clock cycles of system clock; 3: The SSC output bit 1’s basic period will be 4 clock cycles of system clock; 4: The SSC output bit 1’s basic period will be 5 clock cycles of system clock; 5: The SSC output bit 1’s basic period will be 6 clock cycles of system clock; 6: The SSC output bit 1’s basic period will be 7 clock cycles of system clock; 7: The SSC output bit 1’s basic period will be 8 clock cycles of system clock; 8: The SSC output bit 1’s basic period will be 9 clock cycles of system clock; 9: The SSC output bit 1’s basic period will be 10 clock cycles of system clock; 10: The SSC output bit 1’s basic period will be 11 clock cycles of system clock; 11: The SSC output bit 1’s basic period will be 12 clock cycles of system clock; 12: The SSC output bit 1’s basic period will be 13 clock cycles of system clock; 13: The SSC output bit 1’s basic period will be 14 clock cycles of system clock; 14: The SSC output bit 1’s basic period will be 15 clock cycles of system clock; 15: The SSC output bit 1’s basic period will be 16 clock cycles of system clock

pub const fn set_base_nocharge_num(&mut self, val: u8)

BASE_NOCHARGE_NUM. Encodings: 0: The SSC output bit 1’s basic period will be 1 clock cycle of system clock; 1: The SSC output bit 1’s basic period will be 2 clock cycles of system clock; 2: The SSC output bit 1’s basic period will be 3 clock cycles of system clock; 3: The SSC output bit 1’s basic period will be 4 clock cycles of system clock; 4: The SSC output bit 1’s basic period will be 5 clock cycles of system clock; 5: The SSC output bit 1’s basic period will be 6 clock cycles of system clock; 6: The SSC output bit 1’s basic period will be 7 clock cycles of system clock; 7: The SSC output bit 1’s basic period will be 8 clock cycles of system clock; 8: The SSC output bit 1’s basic period will be 9 clock cycles of system clock; 9: The SSC output bit 1’s basic period will be 10 clock cycles of system clock; 10: The SSC output bit 1’s basic period will be 11 clock cycles of system clock; 11: The SSC output bit 1’s basic period will be 12 clock cycles of system clock; 12: The SSC output bit 1’s basic period will be 13 clock cycles of system clock; 13: The SSC output bit 1’s basic period will be 14 clock cycles of system clock; 14: The SSC output bit 1’s basic period will be 15 clock cycles of system clock; 15: The SSC output bit 1’s basic period will be 16 clock cycles of system clock

pub const fn charge_num(&self) -> u8

CHARGE_NUM. Encodings: 0: The SSC output bit 0’s period will be 1 clock cycle of system clock; 1: The SSC output bit 0’s period will be 2 clock cycles of system clock; 2: The SSC output bit 0’s period will be 3 clock cycles of system clock; 3: The SSC output bit 0’s period will be 4 clock cycles of system clock; 4: The SSC output bit 0’s period will be 5 clock cycles of system clock; 5: The SSC output bit 0’s period will be 6 clock cycles of system clock; 6: The SSC output bit 0’s period will be 7 clock cycles of system clock; 7: The SSC output bit 0’s period will be 8 clock cycles of system clock; 8: The SSC output bit 0’s period will be 9 clock cycles of system clock; 9: The SSC output bit 0’s period will be 10 clock cycles of system clock; 10: The SSC output bit 0’s period will be 11 clock cycles of system clock; 11: The SSC output bit 0’s period will be 12 clock cycles of system clock; 12: The SSC output bit 0’s period will be 13 clock cycles of system clock; 13: The SSC output bit 0’s period will be 14 clock cycles of system clock; 14: The SSC output bit 0’s period will be 15 clock cycles of system clock; 15: The SSC output bit 0’s period will be 16 clock cycles of system clock

pub const fn set_charge_num(&mut self, val: u8)

CHARGE_NUM. Encodings: 0: The SSC output bit 0’s period will be 1 clock cycle of system clock; 1: The SSC output bit 0’s period will be 2 clock cycles of system clock; 2: The SSC output bit 0’s period will be 3 clock cycles of system clock; 3: The SSC output bit 0’s period will be 4 clock cycles of system clock; 4: The SSC output bit 0’s period will be 5 clock cycles of system clock; 5: The SSC output bit 0’s period will be 6 clock cycles of system clock; 6: The SSC output bit 0’s period will be 7 clock cycles of system clock; 7: The SSC output bit 0’s period will be 8 clock cycles of system clock; 8: The SSC output bit 0’s period will be 9 clock cycles of system clock; 9: The SSC output bit 0’s period will be 10 clock cycles of system clock; 10: The SSC output bit 0’s period will be 11 clock cycles of system clock; 11: The SSC output bit 0’s period will be 12 clock cycles of system clock; 12: The SSC output bit 0’s period will be 13 clock cycles of system clock; 13: The SSC output bit 0’s period will be 14 clock cycles of system clock; 14: The SSC output bit 0’s period will be 15 clock cycles of system clock; 15: The SSC output bit 0’s period will be 16 clock cycles of system clock

pub const fn ssc_control_reverse(&self) -> bool

SSC_CONTROL_REVERSE. Encodings: 0: Keep the polarity of the SSC output bit; 1: Reverse the polarity of the SSC output bit

pub const fn set_ssc_control_reverse(&mut self, val: bool)

SSC_CONTROL_REVERSE. Encodings: 0: Keep the polarity of the SSC output bit; 1: Reverse the polarity of the SSC output bit

pub const fn ssc_mode(&self) -> Ssc0SscMode

SSC_MODE. Encodings: 0: Using PRBS method generating SSC output bit; 1: Using up-down counter generating SSC output bit; 2: SSC function is disabled; 3: NC

pub const fn set_ssc_mode(&mut self, val: Ssc0SscMode)

SSC_MODE. Encodings: 0: Using PRBS method generating SSC output bit; 1: Using up-down counter generating SSC output bit; 2: SSC function is disabled; 3: NC

pub const fn prbs_outsel(&self) -> u8

Primitive polynomial order 2..15 in PRBS mode; 0 and 1 are NC.

pub const fn set_prbs_outsel(&mut self, val: u8)

Primitive polynomial order 2..15 in PRBS mode; 0 and 1 are NC.

Trait Implementations

impl Clone for Ssc0

fn clone(&self) -> Ssc0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ssc0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Ssc0

fn default() -> Ssc0

Returns the “default value” for a type.

impl PartialEq for Ssc0

fn eq(&self, other: &Ssc0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ssc0

impl Eq for Ssc0

impl StructuralPartialEq for Ssc0