Struct Flexio 

pub struct Flexio { /* private fields */ }

Flexible I/O: four shifters, four timers, 32 pins, four external triggers. Register accesses are 32-bit even when a field is narrower.

Implementations

impl Flexio

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn verid(self) -> Reg<Verid, R>

Version ID.

pub const fn param(self) -> Reg<Param, R>

Parameter.

pub const fn ctrl(self) -> Reg<Ctrl, RW>

FLEXIO Control. FASTACC requires functional clock >= bus clock. SWRST leaves CTRL intact; other accesses are ignored until software clears it and clock-domain reset completes.

pub const fn pin(self) -> Reg<Pin, R>

Pin State.

pub const fn shiftstat(self) -> Reg<Shiftstat, RW>

Shifter Status. Per-shifter flag mask; clearing semantics depend on shifter mode. Do not assume every mode supports write-one-to-clear.

pub const fn shifterr(self) -> Reg<Shifterr, RW>

Shifter Error. Per-shifter error mask, write one to clear. In Match Continuous mode, reading the corresponding SHIFTBUF additionally clears SEF; reading SHIFTERR itself is not that clearing operation.

pub const fn timstat(self) -> Reg<Timstat, RW>

Timer Status Flag.

pub const fn shiftsien(self) -> Reg<Shiftsien, RW>

Shifter Status Interrupt Enable.

pub const fn shifteien(self) -> Reg<Shifteien, RW>

Shifter Error Interrupt Enable.

pub const fn timien(self) -> Reg<Timien, RW>

Timer Interrupt Enable.

pub const fn shiftsden(self) -> Reg<Shiftsden, RW>

Shifter Status DMA Enable.

pub const fn timersden(self) -> Reg<Timersden, RW>

Timer Status DMA Enable. Timer DMA requests remain asserted until the required TIMCMP read/write is performed.

pub const fn shiftstate(self) -> Reg<Shiftstate, RW>

Shifter State.

pub const fn trgstat(self) -> Reg<Trgstat, RW>

Trigger Status.

pub const fn trigien(self) -> Reg<Trigien, RW>

External Trigger Interrupt Enable.

pub const fn pinstat(self) -> Reg<Pinstat, RW>

Pin Status.

pub const fn pinien(self) -> Reg<Pinien, RW>

Pin Interrupt Enable.

pub const fn pinren(self) -> Reg<Pinren, RW>

Pin Rising Edge Enable.

pub const fn pinfen(self) -> Reg<Pinfen, RW>

Pin Falling Edge Enable.

pub const fn pinoutd(self) -> Reg<Pinoutd, RW>

Pin Output Data.

pub const fn pinoute(self) -> Reg<Pinoute, RW>

Pin Output Enable.

pub const fn pinoutdis(self) -> Reg<Pinoutdis, RW>

Direct pin command: clears both pin output data and output enable.

pub const fn pinoutclr(self) -> Reg<Pinoutclr, RW>

Direct pin command: clears data and enables output for the selected pins.

pub const fn pinoutset(self) -> Reg<Pinoutset, RW>

Direct pin command: sets data and enables output for the selected pins.

pub const fn pinouttog(self) -> Reg<Pinouttog, RW>

Direct pin command: toggles data and enables output for the selected pins.

pub const fn shiftctl(self, n: usize) -> Reg<Shiftctl, RW>

Shifter Control.

pub const fn shiftcfg(self, n: usize) -> Reg<Shiftcfg, RW>

Shifter Configuration.

pub const fn shiftbuf(self, n: usize) -> Reg<Shiftbuf, RW>

Shifter Buffer. Receive/Match Store reads require SSF set. Swapped buffer views alias this buffer; they are not independent storage.

pub const fn shiftbufbis(self, n: usize) -> Reg<Shiftbufbis, RW>

Shifter Buffer Bit Swapped.

pub const fn shiftbufbys(self, n: usize) -> Reg<Shiftbufbys, RW>

Shifter Buffer Byte Swapped.

pub const fn shiftbufbbs(self, n: usize) -> Reg<Shiftbufbbs, RW>

Shifter Buffer Bit Byte Swapped.

pub const fn timctl(self, n: usize) -> Reg<Timctl, RW>

Timer Control.

pub const fn timcfg(self, n: usize) -> Reg<Timcfg, RW>

Timer Configuration.

pub const fn timcmp(self, n: usize) -> Reg<Timcmp, RW>

Timer Compare. Input-capture reads require TSF set. The data field is 16-bit, but accesses remain 32-bit.

pub const fn shiftbufnbs(self, n: usize) -> Reg<Shiftbufnbs, RW>

Shifter Buffer Nibble Byte Swapped.

pub const fn shiftbufhws(self, n: usize) -> Reg<Shiftbufhws, RW>

Shifter Buffer Halfword Swapped.

pub const fn shiftbufnis(self, n: usize) -> Reg<Shiftbufnis, RW>

Shifter Buffer Nibble Swapped.

pub const fn shiftbufoes(self, n: usize) -> Reg<Shiftbufoes, RW>

Shifter Buffer Odd Even Swapped.

pub const fn shiftbufeos(self, n: usize) -> Reg<Shiftbufeos, RW>

Shifter Buffer Even Odd Swapped.

pub const fn shiftbufhbs(self, n: usize) -> Reg<Shiftbufhbs, RW>

Shifter Buffer Halfword Byte Swapped.

Trait Implementations

impl Clone for Flexio

fn clone(&self) -> Flexio

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Flexio

fn eq(&self, other: &Flexio) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Flexio

impl Eq for Flexio

impl Send for Flexio

impl StructuralPartialEq for Flexio

impl Sync for Flexio