#[repr(transparent)]pub struct Intenclr(pub u32);Expand description
Interrupt Clear. Alias for clearing the interrupt enables: write one to disable only the intended enables. It does not clear pending event causes.
Tuple Fields§
§0: u32Implementations§
Source§impl Intenclr
impl Intenclr
Sourcepub const fn portint(&self) -> u8
pub const fn portint(&self) -> u8
Port Interrupt. Encodings: 1: Writes 0 to corresponding port interrupt enable
Sourcepub const fn set_portint(&mut self, val: u8)
pub const fn set_portint(&mut self, val: u8)
Port Interrupt. Encodings: 1: Writes 0 to corresponding port interrupt enable
Sourcepub const fn p80int(&self) -> bool
pub const fn p80int(&self) -> bool
Port80 Interrupt. Encodings: 1: Writes 0 to Port80 interrupt enable
Sourcepub const fn set_p80int(&mut self, val: bool)
pub const fn set_p80int(&mut self, val: bool)
Port80 Interrupt. Encodings: 1: Writes 0 to Port80 interrupt enable
Sourcepub const fn busrst(&self) -> bool
pub const fn busrst(&self) -> bool
Bus Reset. Encodings: 1: Writes 0 to reset change interrupt enable
Sourcepub const fn set_busrst(&mut self, val: bool)
pub const fn set_busrst(&mut self, val: bool)
Bus Reset. Encodings: 1: Writes 0 to reset change interrupt enable
Sourcepub const fn irqupd(&self) -> bool
pub const fn irqupd(&self) -> bool
IRQ Update. Encodings: 1: Writes 0 to IRQ completion interrupt enable
Sourcepub const fn set_irqupd(&mut self, val: bool)
pub const fn set_irqupd(&mut self, val: bool)
IRQ Update. Encodings: 1: Writes 0 to IRQ completion interrupt enable
Sourcepub const fn wirechg(&self) -> bool
pub const fn wirechg(&self) -> bool
Wire Change. Encodings: 1: Writes 0 to Wire Change interrupt enable
Sourcepub const fn set_wirechg(&mut self, val: bool)
pub const fn set_wirechg(&mut self, val: bool)
Wire Change. Encodings: 1: Writes 0 to Wire Change interrupt enable
Sourcepub const fn hstall(&self) -> bool
pub const fn hstall(&self) -> bool
Host Stall. Encodings: 1: Writes 0 to HSTALL interrupt enable
Sourcepub const fn set_hstall(&mut self, val: bool)
pub const fn set_hstall(&mut self, val: bool)
Host Stall. Encodings: 1: Writes 0 to HSTALL interrupt enable
Sourcepub const fn crcerr(&self) -> bool
pub const fn crcerr(&self) -> bool
CRC Error. Encodings: 1: Writes 0 to CRCERR interrupt enable
Sourcepub const fn set_crcerr(&mut self, val: bool)
pub const fn set_crcerr(&mut self, val: bool)
CRC Error. Encodings: 1: Writes 0 to CRCERR interrupt enable
Sourcepub const fn set_gpio(&mut self, val: bool)
pub const fn set_gpio(&mut self, val: bool)
GPIO. Encodings: 1: Writes 0 to GPIO interrupt enable
Sourcepub const fn set_cs_int(&mut self, val: bool)
pub const fn set_cs_int(&mut self, val: bool)
CS_INT. Encodings: 0: Disabled; 1: Clear CS falls enable
Sourcepub const fn cportint(&self) -> u8
pub const fn cportint(&self) -> u8
Coprocessor Interrupt. Encodings: 1: Writes 0 to corresponding coprocessor port interrupt enable
Sourcepub const fn set_cportint(&mut self, val: u8)
pub const fn set_cportint(&mut self, val: u8)
Coprocessor Interrupt. Encodings: 1: Writes 0 to corresponding coprocessor port interrupt enable
Sourcepub const fn cp80int(&self) -> bool
pub const fn cp80int(&self) -> bool
Coprocesssor Port80 Interrupt. Encodings: 1: Writes 0 to coprocessor Port80 interrupt enable.
Sourcepub const fn set_cp80int(&mut self, val: bool)
pub const fn set_cp80int(&mut self, val: bool)
Coprocesssor Port80 Interrupt. Encodings: 1: Writes 0 to coprocessor Port80 interrupt enable.
Sourcepub const fn cbusrst(&self) -> bool
pub const fn cbusrst(&self) -> bool
Coprocessor Burst. Encodings: 1: Writes 0 to coprocessor Reset change interrupt enable
Sourcepub const fn set_cbusrst(&mut self, val: bool)
pub const fn set_cbusrst(&mut self, val: bool)
Coprocessor Burst. Encodings: 1: Writes 0 to coprocessor Reset change interrupt enable
Sourcepub const fn cirqupd(&self) -> bool
pub const fn cirqupd(&self) -> bool
Coprocessor IRQ Update. Encodings: 1: Writes 0 to coprocessor IRQ completion interrupt enable
Sourcepub const fn set_cirqupd(&mut self, val: bool)
pub const fn set_cirqupd(&mut self, val: bool)
Coprocessor IRQ Update. Encodings: 1: Writes 0 to coprocessor IRQ completion interrupt enable
Sourcepub const fn cwirechg(&self) -> bool
pub const fn cwirechg(&self) -> bool
Coprocessor Wire Change. Encodings: 1: Writes 0 to coprocessor Wire Change interrupt enable
Sourcepub const fn set_cwirechg(&mut self, val: bool)
pub const fn set_cwirechg(&mut self, val: bool)
Coprocessor Wire Change. Encodings: 1: Writes 0 to coprocessor Wire Change interrupt enable
Sourcepub const fn chstall(&self) -> bool
pub const fn chstall(&self) -> bool
Coprocessor Host Stall. Encodings: 1: Writes 0 to coprocessor HSTALL interrupt enable
Sourcepub const fn set_chstall(&mut self, val: bool)
pub const fn set_chstall(&mut self, val: bool)
Coprocessor Host Stall. Encodings: 1: Writes 0 to coprocessor HSTALL interrupt enable
Sourcepub const fn ccrcerr(&self) -> bool
pub const fn ccrcerr(&self) -> bool
Coprocessor CRC Error. Encodings: 1: Writes 0 to coprocessor CRCERR interrupt enable
Sourcepub const fn set_ccrcerr(&mut self, val: bool)
pub const fn set_ccrcerr(&mut self, val: bool)
Coprocessor CRC Error. Encodings: 1: Writes 0 to coprocessor CRCERR interrupt enable