#[repr(transparent)]pub struct Intstat(pub u32);Expand description
Masked Interrupt Status. Masked interrupt status is MSTAT AND interrupt enables. The memory map and XML mark RW although the function describes a computed status; no undocumented clear-on-write or read side effect is assumed.
Tuple Fields§
§0: u32Implementations§
Source§impl Intstat
impl Intstat
Sourcepub const fn portint(&self) -> u8
pub const fn portint(&self) -> u8
Port Interrupt. Encodings: 0: Disabled; 1: Corresponding port interrupts main processor if it matches IRule
Sourcepub const fn set_portint(&mut self, val: u8)
pub const fn set_portint(&mut self, val: u8)
Port Interrupt. Encodings: 0: Disabled; 1: Corresponding port interrupts main processor if it matches IRule
Sourcepub const fn p80int(&self) -> bool
pub const fn p80int(&self) -> bool
Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupts main processor on update from host
Sourcepub const fn set_p80int(&mut self, val: bool)
pub const fn set_p80int(&mut self, val: bool)
Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupts main processor on update from host
Sourcepub const fn busrst(&self) -> bool
pub const fn busrst(&self) -> bool
Bus Reset. Encodings: 0: Disabled; 1: A change in Bus Reset status interrupts CPU
Sourcepub const fn set_busrst(&mut self, val: bool)
pub const fn set_busrst(&mut self, val: bool)
Bus Reset. Encodings: 0: Disabled; 1: A change in Bus Reset status interrupts CPU
Sourcepub const fn irqupd(&self) -> bool
pub const fn irqupd(&self) -> bool
IRQ Update. Encodings: 0: Disabled; 1: Completion of an IRQ update interrupts CPU
Sourcepub const fn set_irqupd(&mut self, val: bool)
pub const fn set_irqupd(&mut self, val: bool)
IRQ Update. Encodings: 0: Disabled; 1: Completion of an IRQ update interrupts CPU
Sourcepub const fn wirechg(&self) -> bool
pub const fn wirechg(&self) -> bool
Wire Change. Encodings: 0: Disabled; 1: The VWire input change interrupt is enabled and pending for the CPU
Sourcepub const fn set_wirechg(&mut self, val: bool)
pub const fn set_wirechg(&mut self, val: bool)
Wire Change. Encodings: 0: Disabled; 1: The VWire input change interrupt is enabled and pending for the CPU
Sourcepub const fn hstall(&self) -> bool
pub const fn hstall(&self) -> bool
Host Stall. Encodings: 0: Disabled; 1: The HSTALL interrupt is enabled and pending for the CPU
Sourcepub const fn set_hstall(&mut self, val: bool)
pub const fn set_hstall(&mut self, val: bool)
Host Stall. Encodings: 0: Disabled; 1: The HSTALL interrupt is enabled and pending for the CPU
Sourcepub const fn crcerr(&self) -> bool
pub const fn crcerr(&self) -> bool
CRC Error. Encodings: 0: Disabled; 1: The CRC error interrupt is enabled and pending for the CPU
Sourcepub const fn set_crcerr(&mut self, val: bool)
pub const fn set_crcerr(&mut self, val: bool)
CRC Error. Encodings: 0: Disabled; 1: The CRC error interrupt is enabled and pending for the CPU
Sourcepub const fn gpio(&self) -> bool
pub const fn gpio(&self) -> bool
GPIO. Encodings: 0: Disabled; 1: The GPIO input change interrupt is enabled and pending for the CPU
Sourcepub const fn set_gpio(&mut self, val: bool)
pub const fn set_gpio(&mut self, val: bool)
GPIO. Encodings: 0: Disabled; 1: The GPIO input change interrupt is enabled and pending for the CPU
Sourcepub const fn cportint(&self) -> u8
pub const fn cportint(&self) -> u8
Coprocessor Interrupt. Encodings: 0: Disabled; 1: Interrupt is enabled and pending for the coprocessor
Sourcepub const fn set_cportint(&mut self, val: u8)
pub const fn set_cportint(&mut self, val: u8)
Coprocessor Interrupt. Encodings: 0: Disabled; 1: Interrupt is enabled and pending for the coprocessor
Sourcepub const fn cp80int(&self) -> bool
pub const fn cp80int(&self) -> bool
Coprocessor Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupt is enabled and pending for the CPU. Port80 interrupts coprocessor on update from host.
Sourcepub const fn set_cp80int(&mut self, val: bool)
pub const fn set_cp80int(&mut self, val: bool)
Coprocessor Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupt is enabled and pending for the CPU. Port80 interrupts coprocessor on update from host.
Sourcepub const fn cbusrst(&self) -> bool
pub const fn cbusrst(&self) -> bool
Coprocessor Burst. Encodings: 0: Disabled; 1: Bus reset status change interrupt is enabled and pending for the CPU. A change in bus reset status interrupts coprocessor.
Sourcepub const fn set_cbusrst(&mut self, val: bool)
pub const fn set_cbusrst(&mut self, val: bool)
Coprocessor Burst. Encodings: 0: Disabled; 1: Bus reset status change interrupt is enabled and pending for the CPU. A change in bus reset status interrupts coprocessor.
Sourcepub const fn cirqupd(&self) -> bool
pub const fn cirqupd(&self) -> bool
Coprocessor IRQ Update. Encodings: 0: Disabled; 1: IRQ update interrupt is enabled and pending for the CPU.
Sourcepub const fn set_cirqupd(&mut self, val: bool)
pub const fn set_cirqupd(&mut self, val: bool)
Coprocessor IRQ Update. Encodings: 0: Disabled; 1: IRQ update interrupt is enabled and pending for the CPU.
Sourcepub const fn cwirechg(&self) -> bool
pub const fn cwirechg(&self) -> bool
Coprocessor Wire Change. Encodings: 0: Disabled; 1: When one one or more Vwire input has changed, interrupts coprocessor.
Sourcepub const fn set_cwirechg(&mut self, val: bool)
pub const fn set_cwirechg(&mut self, val: bool)
Coprocessor Wire Change. Encodings: 0: Disabled; 1: When one one or more Vwire input has changed, interrupts coprocessor.
Sourcepub const fn chstall(&self) -> bool
pub const fn chstall(&self) -> bool
Coprocessor Host Stall. Encodings: 0: Disabled; 1: When MSTAT[HSTALL] is 1, interrupts coprocessor.
Sourcepub const fn set_chstall(&mut self, val: bool)
pub const fn set_chstall(&mut self, val: bool)
Coprocessor Host Stall. Encodings: 0: Disabled; 1: When MSTAT[HSTALL] is 1, interrupts coprocessor.
Sourcepub const fn ccrcerr(&self) -> bool
pub const fn ccrcerr(&self) -> bool
Coprocessor CRC Error. Encodings: 0: Disabled; 1: When a CRC error detected, interrupts coprocessor.
Sourcepub const fn set_ccrcerr(&mut self, val: bool)
pub const fn set_ccrcerr(&mut self, val: bool)
Coprocessor CRC Error. Encodings: 0: Disabled; 1: When a CRC error detected, interrupts coprocessor.