Struct DmaCh0Control

Source

#[repr(transparent)]
pub struct DmaCh0Control(pub u32);

Expand description

F70RM Rev. 1 section 51.7.5.2; manual text line 155697.

Tuple Fields§

§0: u32

Implementations§

Source §

impl DmaCh0Control

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pub const fn pblx8(&self) -> bool

8xPBL mode. - 1: Indicates that the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. 0b - 8xPBL mode is disabled 1b - 8xPBL mode is enabled

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pub const fn set_pblx8(&mut self, val: bool)

8xPBL mode. - 1: Indicates that the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. 0b - 8xPBL mode is disabled 1b - 8xPBL mode is enabled

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pub const fn dsl(&self) -> u8

Descriptor Skip Length. This bit specifies the Word (32-bit) number of locations to skip between two descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous.

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pub const fn set_dsl(&mut self, val: u8)

Descriptor Skip Length. This bit specifies the Word (32-bit) number of locations to skip between two descriptors. The address skipping starts from the end of the current descriptor to the start of the next descriptor. When the DSL value is equal to zero, the DMA takes the descriptor table as contiguous.

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pub const fn dro(&self) -> bool

Descriptor Re-fetch when Own bit is 0. When this bit is set and OWN bit of a descriptor is 0, an additional attempt is made by the DMA engine to fetch the descriptor. If the OWN bit is still 0, Transmit/Receive Buffer Unavailable (TBU/RBU) interrupt is generated and the DMA goes into SUSPEND state until Tail pointer register is updated by the application. When this bit is low, DMA engine goes into SUSPEND mode as soon as it finds OWN bit to be 0.

Source

pub const fn set_dro(&mut self, val: bool)

Descriptor Re-fetch when Own bit is 0. When this bit is set and OWN bit of a descriptor is 0, an additional attempt is made by the DMA engine to fetch the descriptor. If the OWN bit is still 0, Transmit/Receive Buffer Unavailable (TBU/RBU) interrupt is generated and the DMA goes into SUSPEND state until Tail pointer register is updated by the application. When this bit is low, DMA engine goes into SUSPEND mode as soon as it finds OWN bit to be 0.