Struct DmaCh0RxControl

Source

#[repr(transparent)]
pub struct DmaCh0RxControl(pub u32);

Expand description

F70RM Rev. 1 section 51.7.5.4; manual text line 155960.

Tuple Fields§

§0: u32

Implementations§

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impl DmaCh0RxControl

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pub const fn sr(&self) -> bool

Start or Stop Receive. - 1: DMA attempts to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: – The current position in the list This is the address set by the DMA_CH0_RxDesc_List_Address register. – The position at which the Rx process was previously stopped If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the DMA_CH0_Status register is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the DMA_CH0_RxDesc_List_Address register, the DMA behavior is unpredictable. - 0: Rx DMA operation stops after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state. NOTE This field is not testable by an automated register test. 0b - Stop Receive 1b - Start Receive

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pub const fn set_sr(&mut self, val: bool)

Start or Stop Receive. - 1: DMA attempts to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: – The current position in the list This is the address set by the DMA_CH0_RxDesc_List_Address register. – The position at which the Rx process was previously stopped If the DMA does not own the current descriptor, the reception is suspended and the RBU bit of the DMA_CH0_Status register is set. The Start Receive command is effective only when the reception is stopped. If the command is issued before setting the DMA_CH0_RxDesc_List_Address register, the DMA behavior is unpredictable. - 0: Rx DMA operation stops after the transfer of the current packet. The next descriptor position in the Receive list is saved, and it becomes the current position after the Rx process is restarted. The Stop Receive command is effective only when the Rx process is in the Running (waiting for Rx packet) or Suspended state. NOTE This field is not testable by an automated register test. 0b - Stop Receive 1b - Start Receive

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pub const fn rbsz_x_0(&self) -> u8

Read-only. Receive Buffer size Low. RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field. This field is of width 2 bits. This field is read-only (RO).

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pub const fn set_rbsz_x_0(&mut self, val: u8)

Read-only. Receive Buffer size Low. RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field. This field is of width 2 bits. This field is read-only (RO).

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pub const fn rbsz_13_y(&self) -> u16

Receive Buffer size High. RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is applicable to payload buffers when split headers are enabled. Note: The buffer size must be a multiple of 4. This is required even if the value of buffer address pointer is not aligned to data bus width. Hence the lower RBSZ_x_0 bits are read-only and the value is considered as all-zero. Thus the RBSZ_13_y indicates the buffer size in terms of locations.

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pub const fn set_rbsz_13_y(&mut self, val: u16)

Receive Buffer size High. RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is applicable to payload buffers when split headers are enabled. Note: The buffer size must be a multiple of 4. This is required even if the value of buffer address pointer is not aligned to data bus width. Hence the lower RBSZ_x_0 bits are read-only and the value is considered as all-zero. Thus the RBSZ_13_y indicates the buffer size in terms of locations.

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pub const fn rxpbl(&self) -> u8

Receive Programmable Burst Length. These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: 1. Set the 8xPBL mode in the DMA_CH0_Control register. 2. Set the RxPBL. Note: The maximum value of RxPBL must be less than or equal to half the Rx Queue size (RQS field of MTL_RxQ0_Operation_Mode register) in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the Rx DMA is transferring a block of data. For example, in 32-bit data width configurations the total locations in Rx Queue of size 512 bytes is 128, so RxPBL and 8xPBL needs to be programmed to less than or equal to 64.

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pub const fn set_rxpbl(&mut self, val: u8)

Receive Programmable Burst Length. These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: 1. Set the 8xPBL mode in the DMA_CH0_Control register. 2. Set the RxPBL. Note: The maximum value of RxPBL must be less than or equal to half the Rx Queue size (RQS field of MTL_RxQ0_Operation_Mode register) in terms of beats. This is required so that the Rx Queue has space to store at least another Rx PBL worth of data while the Rx DMA is transferring a block of data. For example, in 32-bit data width configurations the total locations in Rx Queue of size 512 bytes is 128, so RxPBL and 8xPBL needs to be programmed to less than or equal to 64.

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pub const fn eric(&self) -> bool

Early Receive Interrupt Control. - 1: Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer. - 0: Early Receive Interrupt (ERI) status is set only after a complete buffer is filled up by the RxDMA. 0b - Early Receive Interrupt is disabled 1b - Early Receive Interrupt is enabled

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pub const fn set_eric(&mut self, val: bool)

Early Receive Interrupt Control. - 1: Early Receive Interrupt (ERI) status is set after the completion of every burst transfer of data from the Rx DMA to the buffer. - 0: Early Receive Interrupt (ERI) status is set only after a complete buffer is filled up by the RxDMA. 0b - Early Receive Interrupt is disabled 1b - Early Receive Interrupt is enabled

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pub const fn rpf(&self) -> bool

Rx Packet Flush.. - 1: The QoS controller automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel, when it is stopped. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this RxDMA was stopped, still get flushed out. The packets received by the MAC only after the DMA is re-started is routed to the Rx DMA. The flushing is done on the Read side of the Rx Queue. When the packet is duplicated to multiple Rx DMA, it is flushed by the Rx DMA to which it is routed only when it is stopped to prevent head-of-line blocking. The packet duplicated to multiple Rx DMA is not flushed when the Rx DMA is re-started, irrespective of whether the packet was received during one or more Rx DMAs were stopped. - 0: The QoS controller does not flush the packet in the Rx Queue destined to this RxDMA Channel when it is in STOP state. This might cause head-of-line blocking in the corresponding RxQueue. Note: The stopping of packet flow from a Rx DMA Channel to the application by setting RPF works only when there is one-to-one mapping of Rx Queue to Rx DMA channels. In Dynamic mapping mode, setting RPF bit in any DMA_CH0_Rx_Control register might flush packets from unintended Rx Queues which are destined to the stopped Rx DMA Channel. 0b - Rx Packet Flush is disabled 1b - Rx Packet Flush is enabled

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pub const fn set_rpf(&mut self, val: bool)

Rx Packet Flush.. - 1: The QoS controller automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel, when it is stopped. When this bit remains set and the DMA is re-started by the software driver, the packets residing in the Rx Queues that were received when this RxDMA was stopped, still get flushed out. The packets received by the MAC only after the DMA is re-started is routed to the Rx DMA. The flushing is done on the Read side of the Rx Queue. When the packet is duplicated to multiple Rx DMA, it is flushed by the Rx DMA to which it is routed only when it is stopped to prevent head-of-line blocking. The packet duplicated to multiple Rx DMA is not flushed when the Rx DMA is re-started, irrespective of whether the packet was received during one or more Rx DMAs were stopped. - 0: The QoS controller does not flush the packet in the Rx Queue destined to this RxDMA Channel when it is in STOP state. This might cause head-of-line blocking in the corresponding RxQueue. Note: The stopping of packet flow from a Rx DMA Channel to the application by setting RPF works only when there is one-to-one mapping of Rx Queue to Rx DMA channels. In Dynamic mapping mode, setting RPF bit in any DMA_CH0_Rx_Control register might flush packets from unintended Rx Queues which are destined to the stopped Rx DMA Channel. 0b - Rx Packet Flush is disabled 1b - Rx Packet Flush is enabled