Struct DmaCh0Status 

#[repr(transparent)]
pub struct DmaCh0Status(pub u32);

F70RM Rev. 1 section 51.7.5.17; manual text line 157015.

Tuple Fields

0: u32

Implementations

impl DmaCh0Status

pub const fn ti(&self) -> bool

Transmit Interrupt. This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Transmit Interrupt status not detected 1b - Transmit Interrupt status detected

pub const fn set_ti(&mut self, val: bool)

Transmit Interrupt. This bit indicates that the packet transmission is complete. When transmission is complete, Bit 31 of TDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Transmit Interrupt status not detected 1b - Transmit Interrupt status detected

pub const fn tps(&self) -> bool

Transmit Process Stopped. This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Transmit Process Stopped status not detected 1b - Transmit Process Stopped status detected

pub const fn set_tps(&mut self, val: bool)

Transmit Process Stopped. This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Transmit Process Stopped status not detected 1b - Transmit Process Stopped status detected

pub const fn tbu(&self) -> bool

Transmit Buffer Unavailable. This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0-DMA_Debug_Status2 register explains the Transmit Process state transitions. To resume processing the Transmit descriptors, the application must do the following: - Change the ownership of the descriptor by setting Bit 31 of TDES3. - Issue a Transmit Poll Demand command. For ring mode, the application must advance the Transmit Descriptor Tail Pointer register of a channel. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Transmit Buffer Unavailable status not detected 1b - Transmit Buffer Unavailable status detected

pub const fn set_tbu(&mut self, val: bool)

Transmit Buffer Unavailable. This bit indicates that the application owns the next descriptor in the Transmit list, and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0-DMA_Debug_Status2 register explains the Transmit Process state transitions. To resume processing the Transmit descriptors, the application must do the following: - Change the ownership of the descriptor by setting Bit 31 of TDES3. - Issue a Transmit Poll Demand command. For ring mode, the application must advance the Transmit Descriptor Tail Pointer register of a channel. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Transmit Buffer Unavailable status not detected 1b - Transmit Buffer Unavailable status detected

pub const fn ri(&self) -> bool

Receive Interrupt. This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. The reception remains in the Running state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Receive Interrupt status not detected 1b - Receive Interrupt status detected

pub const fn set_ri(&mut self, val: bool)

Receive Interrupt. This bit indicates that the packet reception is complete. When packet reception is complete, Bit 31 of RDES3 is reset in the last descriptor, and the specific packet status information is updated in the descriptor. The reception remains in the Running state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Receive Interrupt status not detected 1b - Receive Interrupt status detected

pub const fn rbu(&self) -> bool

Receive Buffer Unavailable. This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application must change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application must advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Receive Buffer Unavailable status not detected 1b - Receive Buffer Unavailable status detected

pub const fn set_rbu(&mut self, val: bool)

Receive Buffer Unavailable. This bit indicates that the application owns the next descriptor in the Receive list, and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors, the application must change the ownership of the descriptor and issue a Receive Poll Demand command. If this command is not issued, the Rx process resumes when the next recognized incoming packet is received. In ring mode, the application must advance the Receive Descriptor Tail Pointer register of a channel. This bit is set only when the DMA owns the previous Rx descriptor. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Receive Buffer Unavailable status not detected 1b - Receive Buffer Unavailable status detected

pub const fn rps(&self) -> bool

Receive Process Stopped. This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Receive Process Stopped status not detected 1b - Receive Process Stopped status detected

pub const fn set_rps(&mut self, val: bool)

Receive Process Stopped. This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Receive Process Stopped status not detected 1b - Receive Process Stopped status detected

pub const fn rwt(&self) -> bool

Receive Watchdog Timeout. This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. NOTE This field is not testable by an automated register test. 0b - Receive Watchdog Timeout status not detected 1b - Receive Watchdog Timeout status detected

pub const fn set_rwt(&mut self, val: bool)

Receive Watchdog Timeout. This bit is asserted when a packet with length greater than 2,048 bytes (10,240 bytes when Jumbo Packet mode is enabled) is received. NOTE This field is not testable by an automated register test. 0b - Receive Watchdog Timeout status not detected 1b - Receive Watchdog Timeout status detected

pub const fn eti(&self) -> bool

Early Transmit Interrupt. This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configurations supporting ERIC: - ETIC = 0: This bit is set only after the Tx DMA has transferred a complete packet to MTL. - ETIC = 1: This bit is set after completion of (partial) packet data transfer from buffers in the Transmit descriptor in which IOC = 1. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Early Transmit Interrupt status not detected 1b - Early Transmit Interrupt status detected

pub const fn set_eti(&mut self, val: bool)

Early Transmit Interrupt. This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configurations supporting ERIC: - ETIC = 0: This bit is set only after the Tx DMA has transferred a complete packet to MTL. - ETIC = 1: This bit is set after completion of (partial) packet data transfer from buffers in the Transmit descriptor in which IOC = 1. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Early Transmit Interrupt status not detected 1b - Early Transmit Interrupt status detected

pub const fn eri(&self) -> bool

Early Receive Interrupt. This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configurations supporting ERIC, - ERIC = 0: This bit is set only after the Rx DMA has completely filled up a receive buffer with packet data. - ERIC = 1: This bit is set after every burst transfer of data from the Rx DMA to the buffer. The setting of RI bit automatically clears this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Early Receive Interrupt status not detected 1b - Early Receive Interrupt status detected

pub const fn set_eri(&mut self, val: bool)

Early Receive Interrupt. This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configurations supporting ERIC, - ERIC = 0: This bit is set only after the Rx DMA has completely filled up a receive buffer with packet data. - ERIC = 1: This bit is set after every burst transfer of data from the Rx DMA to the buffer. The setting of RI bit automatically clears this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Early Receive Interrupt status not detected 1b - Early Receive Interrupt status detected

pub const fn fbe(&self) -> bool

Fatal Bus Error. This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Fatal Bus Error status not detected 1b - Fatal Bus Error status detected

pub const fn set_fbe(&mut self, val: bool)

Fatal Bus Error. This bit indicates that a bus error occurred (as described in the EB field). When this bit is set, the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Fatal Bus Error status not detected 1b - Fatal Bus Error status detected

pub const fn cde(&self) -> bool

Context Descriptor Error. This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one’s descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Context Descriptor Error status not detected 1b - Context Descriptor Error status detected

pub const fn set_cde(&mut self, val: bool)

Context Descriptor Error. This bit indicates that the DMA Tx/Rx engine received a descriptor error, which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one’s descriptor in Tx case and on Rx side it indicates DMA has read a descriptor with either of the buffer address as ones which is considered to be invalid. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Context Descriptor Error status not detected 1b - Context Descriptor Error status detected

pub const fn ais(&self) -> bool

Abnormal Interrupt Summary. Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Abnormal Interrupt Summary status not detected 1b - Abnormal Interrupt Summary status detected

pub const fn set_ais(&mut self, val: bool)

Abnormal Interrupt Summary. Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Abnormal Interrupt Summary status not detected 1b - Abnormal Interrupt Summary status detected

pub const fn nis(&self) -> bool

Normal Interrupt Summary. Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH0_Interrupt_Enable register) affect the Normal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Normal Interrupt Summary status not detected 1b - Normal Interrupt Summary status detected

pub const fn set_nis(&mut self, val: bool)

Normal Interrupt Summary. Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in DMA_CH0_Interrupt_Enable register) affect the Normal Interrupt Summary bit. This is a sticky bit. You must clear this bit (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. NOTE This field is not testable by an automated register test. 0b - Normal Interrupt Summary status not detected 1b - Normal Interrupt Summary status detected

pub const fn teb(&self) -> u8

Read-only. Tx DMA Error Bits. This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. - Bit 18 – 1’b1: Error during data transfer by Tx DMA – 1’b0: No Error during data transfer by Tx DMA - Bit 17 – 1’b1: Error during descriptor access – 1’b0: Error during data buffer access - Bit 16 – 1’b1: Error during read transfer – 1’b0: Error during write transfer This field is valid only when the FBE bit is set. This field does not generate an interrupt. NOTE This field is not testable by an automated register test.

pub const fn set_teb(&mut self, val: u8)

Read-only. Tx DMA Error Bits. This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. - Bit 18 – 1’b1: Error during data transfer by Tx DMA – 1’b0: No Error during data transfer by Tx DMA - Bit 17 – 1’b1: Error during descriptor access – 1’b0: Error during data buffer access - Bit 16 – 1’b1: Error during read transfer – 1’b0: Error during write transfer This field is valid only when the FBE bit is set. This field does not generate an interrupt. NOTE This field is not testable by an automated register test.

pub const fn reb(&self) -> u8

Read-only. Rx DMA Error Bits. This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. - Bit 21 – 1’b1: Error during data transfer by Rx DMA – 1’b0: No Error during data transfer by Rx DMA - Bit 20 – 1’b1: Error during descriptor access – 1’b0: Error during data buffer access - Bit 19 – 1’b1: Error during read transfer – 1’b0: Error during write transfer This field is valid only when the FBE bit is set. This field does not generate an interrupt. NOTE This field is not testable by an automated register test.

pub const fn set_reb(&mut self, val: u8)

Read-only. Rx DMA Error Bits. This field indicates the type of error that caused a Bus Error. For example, error response on the AHB interface. - Bit 21 – 1’b1: Error during data transfer by Rx DMA – 1’b0: No Error during data transfer by Rx DMA - Bit 20 – 1’b1: Error during descriptor access – 1’b0: Error during data buffer access - Bit 19 – 1’b1: Error during read transfer – 1’b0: Error during write transfer This field is valid only when the FBE bit is set. This field does not generate an interrupt. NOTE This field is not testable by an automated register test.

Trait Implementations

impl Clone for DmaCh0Status

fn clone(&self) -> DmaCh0Status

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DmaCh0Status

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for DmaCh0Status

fn default() -> DmaCh0Status

Returns the “default value” for a type.

impl PartialEq for DmaCh0Status

fn eq(&self, other: &DmaCh0Status) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for DmaCh0Status

impl Eq for DmaCh0Status

impl StructuralPartialEq for DmaCh0Status