#[repr(transparent)]pub struct DmaMode(pub u32);Expand description
F70RM Rev. 1 section 51.7.4.2; manual text line 155024.
Tuple Fields§
§0: u32Implementations§
Source§impl DmaMode
impl DmaMode
Sourcepub const fn swr(&self) -> bool
pub const fn swr(&self) -> bool
Software Reset. - 1: Indicates that the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all the clock domains of the QoS controller. Before reprogramming the Qos controller register, read a value of zero in this bit. After writing 1 to this bit, wait for at the least 4 CSR clock cycles, before reading this bit. Note: The reset operation is complete only when the QoS controller has de-asserted all resets in all active clock domains. Therefore, it is essential that all PHY input clocks of the selected PHY interface are present for the completion of the software reset. The time required to complete the software reset operation depends on the frequency of the slowest active clock. Access restrictions apply. - Initiates the software reset when application writes 1. - MAC writes 0 after the software reset is complete. - MAC ignores when application writes 0. NOTE This field is not testable by an automated register test. 0b - Software Reset is disabled 1b - Software Reset is enabled
Sourcepub const fn set_swr(&mut self, val: bool)
pub const fn set_swr(&mut self, val: bool)
Software Reset. - 1: Indicates that the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all the clock domains of the QoS controller. Before reprogramming the Qos controller register, read a value of zero in this bit. After writing 1 to this bit, wait for at the least 4 CSR clock cycles, before reading this bit. Note: The reset operation is complete only when the QoS controller has de-asserted all resets in all active clock domains. Therefore, it is essential that all PHY input clocks of the selected PHY interface are present for the completion of the software reset. The time required to complete the software reset operation depends on the frequency of the slowest active clock. Access restrictions apply. - Initiates the software reset when application writes 1. - MAC writes 0 after the software reset is complete. - MAC ignores when application writes 0. NOTE This field is not testable by an automated register test. 0b - Software Reset is disabled 1b - Software Reset is enabled
Sourcepub const fn da(&self) -> bool
pub const fn da(&self) -> bool
DMA Tx or Rx Arbitration Scheme. This bit specifies the arbitration scheme for the Transmit and Receive paths of all channels: - 0: Weighted Round-Robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit. - 1: Fixed Priority The Tx path has priority over the Rx path when the TXPR bit is 1. Otherwise, the Rx path has priority over the Tx path. 0b - Weighted Round-Robin with Rx:Tx or Tx:Rx 1b - Fixed Priority
Sourcepub const fn set_da(&mut self, val: bool)
pub const fn set_da(&mut self, val: bool)
DMA Tx or Rx Arbitration Scheme. This bit specifies the arbitration scheme for the Transmit and Receive paths of all channels: - 0: Weighted Round-Robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits[14:12] and the priority weight is specified in the TXPR bit. - 1: Fixed Priority The Tx path has priority over the Rx path when the TXPR bit is 1. Otherwise, the Rx path has priority over the Tx path. 0b - Weighted Round-Robin with Rx:Tx or Tx:Rx 1b - Fixed Priority
Sourcepub const fn arbc(&self) -> bool
pub const fn arbc(&self) -> bool
ARBC is Synopsys Reserved, This field must be set to “0”.. - This field is reserved for Synopsys Internal use, and must always be set to “0” unless instructed by Synopsys. - Setting this field to “1” might cause unexpected behavior in the HW. 0b - Synopsys reserved field disabled 1b - Synopsys reserved field enabled up on Synopsys request
Sourcepub const fn set_arbc(&mut self, val: bool)
pub const fn set_arbc(&mut self, val: bool)
ARBC is Synopsys Reserved, This field must be set to “0”.. - This field is reserved for Synopsys Internal use, and must always be set to “0” unless instructed by Synopsys. - Setting this field to “1” might cause unexpected behavior in the HW. 0b - Synopsys reserved field disabled 1b - Synopsys reserved field enabled up on Synopsys request
Sourcepub const fn txpr(&self) -> bool
pub const fn txpr(&self) -> bool
Transmit Priority. - 1: Indicates that the Tx DMA has priority over the Rx DMA during arbitration for the system-side bus. 0b - Transmit Priority is disabled 1b - Transmit Priority is enabled
Sourcepub const fn set_txpr(&mut self, val: bool)
pub const fn set_txpr(&mut self, val: bool)
Transmit Priority. - 1: Indicates that the Tx DMA has priority over the Rx DMA during arbitration for the system-side bus. 0b - Transmit Priority is disabled 1b - Transmit Priority is enabled
Sourcepub const fn pr(&self) -> u8
pub const fn pr(&self) -> u8
Priority Ratio. These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. 000b - The priority ratio is 1:1 001b - The priority ratio is 2:1 010b - The priority ratio is 3:1 011b - The priority ratio is 4:1 100b - The priority ratio is 5:1 101b - The priority ratio is 6:1 110b - The priority ratio is 7:1 111b - The priority ratio is 8:1
Sourcepub const fn set_pr(&mut self, val: u8)
pub const fn set_pr(&mut self, val: u8)
Priority Ratio. These bits control the priority ratio in weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when the DA bit is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether the TXPR bit is reset or set. 000b - The priority ratio is 1:1 001b - The priority ratio is 2:1 010b - The priority ratio is 3:1 011b - The priority ratio is 4:1 100b - The priority ratio is 5:1 101b - The priority ratio is 6:1 110b - The priority ratio is 7:1 111b - The priority ratio is 8:1
Sourcepub const fn intm(&self) -> u8
pub const fn intm(&self) -> u8
Interrupt Mode. This field defines the interrupt mode of the QoS controller. The behavior of the following outputs change depending on the following settings: - sbd_perch_tx_intr_o[] (Transmit Per Channel Interrupt) - sbd_perch_rx_intr_o[] (Receive Per Channel Interrupt) - sbd_intr_o (Common Interrupt) It also changes the behavior of the RI/TI bits in the DMA_CH(#i)Status. - 00: sbd_perch* are pulse signals for each TX/RX packet transfer completion events (irrespective of whether corresponding interrupts are enabled) for which IOC bits are enabled in descriptor. sbd_intr_o is also asserted when corresponding interrupts are enabled and cleared only when software clears the corresponding RI/TI status bits. - 01: sbd_perch_* are level signals asserted on TX/RX packet transfer completion event when corresponding interrupts are enabled and de-asserted when the software clears the corresponding RI/TI status bits. The sbd_intr_o is not asserted for these TX/RX packet transfer completion events. - 10: sbd_perch_* are level signals asserted on TX/RX packet transfer completion event when corresponding interrupts are enabled and de-asserted when the software clears the corresponding RI/TI status bits. However, the signal is asserted again if the same event occurred again before it was cleared. The sbd_intr_o is not asserted for these TX/RX packet transfer completion events. - 11: Reserved For more details, see Table “The QoS Controller Transfer Complete Interrupt Behavior”. 00b - See above description 01b - See above description 10b - See above description 11b - Reserved
Sourcepub const fn set_intm(&mut self, val: u8)
pub const fn set_intm(&mut self, val: u8)
Interrupt Mode. This field defines the interrupt mode of the QoS controller. The behavior of the following outputs change depending on the following settings: - sbd_perch_tx_intr_o[] (Transmit Per Channel Interrupt) - sbd_perch_rx_intr_o[] (Receive Per Channel Interrupt) - sbd_intr_o (Common Interrupt) It also changes the behavior of the RI/TI bits in the DMA_CH(#i)Status. - 00: sbd_perch* are pulse signals for each TX/RX packet transfer completion events (irrespective of whether corresponding interrupts are enabled) for which IOC bits are enabled in descriptor. sbd_intr_o is also asserted when corresponding interrupts are enabled and cleared only when software clears the corresponding RI/TI status bits. - 01: sbd_perch_* are level signals asserted on TX/RX packet transfer completion event when corresponding interrupts are enabled and de-asserted when the software clears the corresponding RI/TI status bits. The sbd_intr_o is not asserted for these TX/RX packet transfer completion events. - 10: sbd_perch_* are level signals asserted on TX/RX packet transfer completion event when corresponding interrupts are enabled and de-asserted when the software clears the corresponding RI/TI status bits. However, the signal is asserted again if the same event occurred again before it was cleared. The sbd_intr_o is not asserted for these TX/RX packet transfer completion events. - 11: Reserved For more details, see Table “The QoS Controller Transfer Complete Interrupt Behavior”. 00b - See above description 01b - See above description 10b - See above description 11b - Reserved