Struct MacMdioAddress 

#[repr(transparent)]
pub struct MacMdioAddress(pub u32);

F70RM Rev. 1 section 51.7.1.22; manual text line 151481.

Tuple Fields

0: u32

Implementations

impl MacMdioAddress

pub const fn gb(&self) -> bool

GMII Busy. The application writes 1 to this bit to instruct the SMA to initiate a read or write access to the MDIO slave. The MAC writes 0 to this bit after the MDIO frame transfer is complete. Therefore, the application must modify the fields of the MAC_MDIO_Address and MAC_MDIO_Data registers only when the value in this bit is 0. - For write operation, application must follow these steps: – Write the 16-bit data in the GDl field of the MAC_MDIO_Data register. – Update the RA field of the MAC_MDIO_Data register with the register address of the PHY. NOTE RA field is valid only when C45E field is 1. – Write 1 to this bit - For read operation, application must follow these steps: – Update the RA field of the MAC_MDIO_Data register with the register address of the PHY. NOTE RA field is valid only when C45E field is 1. – Write 1 to this bit – Wait until MAC writes 0 to this bit. When MAC writes 0 to this bit, it implies that the data read from the PHY is available in the GD field of the MAC_MDIO_Data register and the read transfer is complete. NOTE Even if the addressed PHY is not present, there is no change in the functionality of this bit. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0b - GMII Busy is disabled 1b - GMII Busy is enabled

pub const fn set_gb(&mut self, val: bool)

GMII Busy. The application writes 1 to this bit to instruct the SMA to initiate a read or write access to the MDIO slave. The MAC writes 0 to this bit after the MDIO frame transfer is complete. Therefore, the application must modify the fields of the MAC_MDIO_Address and MAC_MDIO_Data registers only when the value in this bit is 0. - For write operation, application must follow these steps: – Write the 16-bit data in the GDl field of the MAC_MDIO_Data register. – Update the RA field of the MAC_MDIO_Data register with the register address of the PHY. NOTE RA field is valid only when C45E field is 1. – Write 1 to this bit - For read operation, application must follow these steps: – Update the RA field of the MAC_MDIO_Data register with the register address of the PHY. NOTE RA field is valid only when C45E field is 1. – Write 1 to this bit – Wait until MAC writes 0 to this bit. When MAC writes 0 to this bit, it implies that the data read from the PHY is available in the GD field of the MAC_MDIO_Data register and the read transfer is complete. NOTE Even if the addressed PHY is not present, there is no change in the functionality of this bit. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0b - GMII Busy is disabled 1b - GMII Busy is enabled

pub const fn c45e(&self) -> bool

Clause 45 PHY Enable. - 1: Clause 45 capable PHY is connected to MDIO. - 0: Clause 22 capable PHY is connected to MDIO. 0b - Clause 45 PHY is disabled 1b - Clause 45 PHY is enabled

pub const fn set_c45e(&mut self, val: bool)

Clause 45 PHY Enable. - 1: Clause 45 capable PHY is connected to MDIO. - 0: Clause 22 capable PHY is connected to MDIO. 0b - Clause 45 PHY is disabled 1b - Clause 45 PHY is enabled

pub const fn goc_0(&self) -> bool

GMII Operation Command 0. This is the lower bit of the operation command to the PHY or RevMII. When in SMA mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY. When only RevMII is selected in configuration this bit is read-only and tied to 1. 0b - GMII Operation Command 0 is disabled 1b - GMII Operation Command 0 is enabled

pub const fn set_goc_0(&mut self, val: bool)

GMII Operation Command 0. This is the lower bit of the operation command to the PHY or RevMII. When in SMA mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY. When only RevMII is selected in configuration this bit is read-only and tied to 1. 0b - GMII Operation Command 0 is disabled 1b - GMII Operation Command 0 is enabled

pub const fn goc_1(&self) -> bool

GMII Operation Command 1. This bit is higher bit of the operation command to the PHY or RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write and Read commands are valid. NOTE This field is not testable by an automated register test. 0b - GMII Operation Command 1 is disabled 1b - GMII Operation Command 1 is enabled

pub const fn set_goc_1(&mut self, val: bool)

GMII Operation Command 1. This bit is higher bit of the operation command to the PHY or RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write and Read commands are valid. NOTE This field is not testable by an automated register test. 0b - GMII Operation Command 1 is disabled 1b - GMII Operation Command 1 is enabled

pub const fn skap(&self) -> bool

Skip Address Packet. - 1: SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set. 0b - Skip Address Packet is disabled 1b - Skip Address Packet is enabled

pub const fn set_skap(&mut self, val: bool)

Skip Address Packet. - 1: SMA does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when C45E is set. 0b - Skip Address Packet is disabled 1b - Skip Address Packet is enabled

pub const fn cr(&self) -> u8

CSR Clock Range. The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26 - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz; MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, the resultant MDC clock is of 12.5 MHz which is beyond the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks: - 1000: CSR clock/4 - 1001: CSR clock/6 - 1010: CSR clock/8 - 1011: CSR clock/10 - 1100: CSR clock/12 - 1101: CSR clock/14 - 1110: CSR clock/16 - 1111: CSR clock/18

pub const fn set_cr(&mut self, val: u8)

CSR Clock Range. The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26 - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz; MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range. When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, the resultant MDC clock is of 12.5 MHz which is beyond the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks: - 1000: CSR clock/4 - 1001: CSR clock/6 - 1010: CSR clock/8 - 1011: CSR clock/10 - 1100: CSR clock/12 - 1101: CSR clock/14 - 1110: CSR clock/16 - 1111: CSR clock/18

pub const fn ntc(&self) -> u8

Number of Trailing Clocks. This field controls the number of trailing clock cycles generated on the gmii_mdc_o (MDC) signal, after the end of MDIO frame transfer. The valid values are 0 to 7. When you program a value of 3’h3 in this field, MAC generates three clock cycles on the MDC line after the end of MDIO frame transfer.

pub const fn set_ntc(&mut self, val: u8)

Number of Trailing Clocks. This field controls the number of trailing clock cycles generated on the gmii_mdc_o (MDC) signal, after the end of MDIO frame transfer. The valid values are 0 to 7. When you program a value of 3’h3 in this field, MAC generates three clock cycles on the MDC line after the end of MDIO frame transfer.

pub const fn rda(&self) -> u8

Register or Device Address. For clause 22 PHY: Specifies the PHY register address of the selected PHY device. - For Clause 45 PHY: Specifies the selected MDIO device. NOTE The value you program in the C45E field determines if the PHY device is clause 45 capable or clause 22 capable.

pub const fn set_rda(&mut self, val: u8)

Register or Device Address. For clause 22 PHY: Specifies the PHY register address of the selected PHY device. - For Clause 45 PHY: Specifies the selected MDIO device. NOTE The value you program in the C45E field determines if the PHY device is clause 45 capable or clause 22 capable.

pub const fn pa(&self) -> u8

Physical Layer Address. Specifies the address of the PHY device, out of the 32 possible PHY devices. NOTE The value you program in the C45E field determines if the PHY device is clause 45 capable or clause 22 capable.

pub const fn set_pa(&mut self, val: u8)

Physical Layer Address. Specifies the address of the PHY device, out of the 32 possible PHY devices. NOTE The value you program in the C45E field determines if the PHY device is clause 45 capable or clause 22 capable.

pub const fn btb(&self) -> bool

Back-to-Back Transactions. 1: If NTC > 0, at the end of the frame transfer, MAC acknowledges the completion of a read or write command before transferring the trailing clocks. So, application can initiate the next command and MAC can execute it immediately without waiting for the transmission of the trailing clocks of the previous frame. - 0: MAC considers the read or write command to be complete, that is, MAC clears the GB field, only after generating the trailing clocks. This mode ensures that the NTC is always generated after each frame. NOTE Program this field with a value 1, only when NTC > 0. 0b - Back to Back transactions disabled 1b - Back to Back transactions enabled

pub const fn set_btb(&mut self, val: bool)

Back-to-Back Transactions. 1: If NTC > 0, at the end of the frame transfer, MAC acknowledges the completion of a read or write command before transferring the trailing clocks. So, application can initiate the next command and MAC can execute it immediately without waiting for the transmission of the trailing clocks of the previous frame. - 0: MAC considers the read or write command to be complete, that is, MAC clears the GB field, only after generating the trailing clocks. This mode ensures that the NTC is always generated after each frame. NOTE Program this field with a value 1, only when NTC > 0. 0b - Back to Back transactions disabled 1b - Back to Back transactions enabled

pub const fn pse(&self) -> bool

Preamble Suppression Enable.. - 1: The SMA suppresses the 32-bit preamble and transmits MDIO packets with only 1 preamble bit. - 0: The MDIO packet always has 32 bits of preamble as defined in the IEEE specifications. 0b - Preamble Suppression disabled 1b - Preamble Suppression enabled

pub const fn set_pse(&mut self, val: bool)

Preamble Suppression Enable.. - 1: The SMA suppresses the 32-bit preamble and transmits MDIO packets with only 1 preamble bit. - 0: The MDIO packet always has 32 bits of preamble as defined in the IEEE specifications. 0b - Preamble Suppression disabled 1b - Preamble Suppression enabled

Trait Implementations

impl Clone for MacMdioAddress

fn clone(&self) -> MacMdioAddress

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for MacMdioAddress

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for MacMdioAddress

fn default() -> MacMdioAddress

Returns the “default value” for a type.

impl PartialEq for MacMdioAddress

fn eq(&self, other: &MacMdioAddress) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for MacMdioAddress

impl Eq for MacMdioAddress

impl StructuralPartialEq for MacMdioAddress