#[repr(transparent)]pub struct MacRxTxStatus(pub u32);Expand description
F70RM Rev. 1 section 51.7.1.13; manual text line 150168.
Tuple Fields§
§0: u32Implementations§
Source§impl MacRxTxStatus
impl MacRxTxStatus
Sourcepub const fn tjt(&self) -> bool
pub const fn tjt(&self) -> bool
Transmit Jabber Timeout. This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the MAC_Configuration register. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No Transmit Jabber Timeout 1b - Transmit Jabber Timeout occurred
Sourcepub const fn set_tjt(&mut self, val: bool)
pub const fn set_tjt(&mut self, val: bool)
Transmit Jabber Timeout. This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the MAC_Configuration register. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No Transmit Jabber Timeout 1b - Transmit Jabber Timeout occurred
Sourcepub const fn ncarr(&self) -> bool
pub const fn ncarr(&self) -> bool
No Carrier. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - Carrier is present 1b - No carrier
Sourcepub const fn set_ncarr(&mut self, val: bool)
pub const fn set_ncarr(&mut self, val: bool)
No Carrier. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - Carrier is present 1b - No carrier
Sourcepub const fn lcarr(&self) -> bool
pub const fn lcarr(&self) -> bool
Loss of Carrier. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - Carrier is present 1b - Loss of carrier
Sourcepub const fn set_lcarr(&mut self, val: bool)
pub const fn set_lcarr(&mut self, val: bool)
Loss of Carrier. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - Carrier is present 1b - Loss of carrier
Sourcepub const fn exdef(&self) -> bool
pub const fn exdef(&self) -> bool
Excessive Deferral. When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or when Jumbo packet is enabled). Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No Excessive deferral 1b - Excessive deferral
Sourcepub const fn set_exdef(&mut self, val: bool)
pub const fn set_exdef(&mut self, val: bool)
Excessive Deferral. When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register, this bit indicates that the transmission ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or when Jumbo packet is enabled). Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No Excessive deferral 1b - Excessive deferral
Sourcepub const fn lcol(&self) -> bool
pub const fn lcol(&self) -> bool
Late Collision. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier Extension in GMII mode). This bit is not valid if the Underflow error occurs. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No collision 1b - Late collision is sensed
Sourcepub const fn set_lcol(&mut self, val: bool)
pub const fn set_lcol(&mut self, val: bool)
Late Collision. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier Extension in GMII mode). This bit is not valid if the Underflow error occurs. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No collision 1b - Late collision is sensed
Sourcepub const fn excol(&self) -> bool
pub const fn excol(&self) -> bool
Excessive Collisions. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the MAC_Configuration register, this bit is set after the first collision and the packet transmission is aborted. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No collision 1b - Excessive collision is sensed
Sourcepub const fn set_excol(&mut self, val: bool)
pub const fn set_excol(&mut self, val: bool)
Excessive Collisions. When the DTXSTS bit is set in the MTL_Operation_Mode register, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the MAC_Configuration register, this bit is set after the first collision and the packet transmission is aborted. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No collision 1b - Excessive collision is sensed
Sourcepub const fn rwt(&self) -> bool
pub const fn rwt(&self) -> bool
Receive Watchdog Timeout. This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register. This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the MAC_Configuration register. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No receive watchdog timeout 1b - Receive watchdog timed out
Sourcepub const fn set_rwt(&mut self, val: bool)
pub const fn set_rwt(&mut self, val: bool)
Receive Watchdog Timeout. This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register. This bit is set when a packet with length greater than 16,383 bytes is received and the WD bit is set in the MAC_Configuration register. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl register is set). Self-set to 1 on internal event. 0b - No receive watchdog timeout 1b - Receive watchdog timed out
Trait Implementations§
Source§impl Clone for MacRxTxStatus
impl Clone for MacRxTxStatus
Source§fn clone(&self) -> MacRxTxStatus
fn clone(&self) -> MacRxTxStatus
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more