#[repr(transparent)]pub struct Smicfg(pub u16);Expand description
F70RM Rev. 1 section 54.5.1.32; manual text line 172931.
Tuple Fields§
§0: u16Implementations§
Source§impl Smicfg
impl Smicfg
Sourcepub const fn speed(&self) -> u8
pub const fn speed(&self) -> u8
Speed. Sets the MDC clock frequency as a ratio of the PCLK frequency: MDC freq = PCLK freq divided by 1/((MII_SPEED+1) × 2)
Sourcepub const fn set_speed(&mut self, val: u8)
pub const fn set_speed(&mut self, val: u8)
Speed. Sets the MDC clock frequency as a ratio of the PCLK frequency: MDC freq = PCLK freq divided by 1/((MII_SPEED+1) × 2)
Sourcepub const fn dispre(&self) -> bool
pub const fn dispre(&self) -> bool
Disable SMI Preamble. Disabled SMI preamble (32 x 1’b1) generation 0b - Disabled 1b - Enabled
Sourcepub const fn set_dispre(&mut self, val: bool)
pub const fn set_dispre(&mut self, val: bool)
Disable SMI Preamble. Disabled SMI preamble (32 x 1’b1) generation 0b - Disabled 1b - Enabled
Sourcepub const fn hold(&self) -> u8
pub const fn hold(&self) -> u8
Hold. Specifies the hold time for the MDIO output. The IEEE802.3 clause 22 specifies a minimum hold time of 10ns 000b - HOLD_1. 1 PCLK cycle (default) 001b - HOLD_2. 2 PCLK cycles 010b - HOLD_3. 3 PCLK cycles 011b - HOLD_4. 4 PCLK cycles 100b - HOLD_5. 5 PCLK cycles 101b - 6 PCLK cycles 6 110b - HOLD_7. 7 PCLK cycles 111b - HOLD_8. 8 PCLK cycles
Sourcepub const fn set_hold(&mut self, val: u8)
pub const fn set_hold(&mut self, val: u8)
Hold. Specifies the hold time for the MDIO output. The IEEE802.3 clause 22 specifies a minimum hold time of 10ns 000b - HOLD_1. 1 PCLK cycle (default) 001b - HOLD_2. 2 PCLK cycles 010b - HOLD_3. 3 PCLK cycles 011b - HOLD_4. 4 PCLK cycles 100b - HOLD_5. 5 PCLK cycles 101b - 6 PCLK cycles 6 110b - HOLD_7. 7 PCLK cycles 111b - HOLD_8. 8 PCLK cycles