Struct Dma1ReqEnable0Clr 

#[repr(transparent)]
pub struct Dma1ReqEnable0Clr(pub u32);

DMA1 Request Enable0

Tuple Fields

0: u32

Implementations

impl Dma1ReqEnable0Clr

pub const fn req1_en1(&self) -> bool

Writing a 1 to REQ1_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req1_en1(&mut self, val: bool)

Writing a 1 to REQ1_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req2_en1(&self) -> bool

Writing a 1 to REQ2_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req2_en1(&mut self, val: bool)

Writing a 1 to REQ2_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req3_en1(&self) -> bool

Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req3_en1(&mut self, val: bool)

Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req4_en1(&self) -> bool

Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req4_en1(&mut self, val: bool)

Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req5_en1(&self) -> bool

Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req5_en1(&mut self, val: bool)

Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req6_en1(&self) -> bool

Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req6_en1(&mut self, val: bool)

Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req7_en1(&self) -> bool

Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req7_en1(&mut self, val: bool)

Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req8_en1(&self) -> bool

Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req8_en1(&mut self, val: bool)

Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req9_en1(&self) -> bool

Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req9_en1(&mut self, val: bool)

Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req10_en1(&self) -> bool

Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req10_en1(&mut self, val: bool)

Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req11_en1(&self) -> bool

Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req11_en1(&mut self, val: bool)

Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req12_en1(&self) -> bool

Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req12_en1(&mut self, val: bool)

Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req13_en1(&self) -> bool

Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req13_en1(&mut self, val: bool)

Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req14_en1(&self) -> bool

Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req14_en1(&mut self, val: bool)

Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req15_en1(&self) -> bool

Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req15_en1(&mut self, val: bool)

Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req16_en1(&self) -> bool

Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req16_en1(&mut self, val: bool)

Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req17_en1(&self) -> bool

Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req17_en1(&mut self, val: bool)

Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req18_en1(&self) -> bool

Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req18_en1(&mut self, val: bool)

Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req19_en1(&self) -> bool

Writing a 1 to REQ19_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req19_en1(&mut self, val: bool)

Writing a 1 to REQ19_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req20_en1(&self) -> bool

Writing a 1 to REQ20_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req20_en1(&mut self, val: bool)

Writing a 1 to REQ20_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req21_en1(&self) -> bool

Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req21_en1(&mut self, val: bool)

Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req22_en1(&self) -> bool

Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req22_en1(&mut self, val: bool)

Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req23_en1(&self) -> bool

Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req23_en1(&mut self, val: bool)

Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req24_en1(&self) -> bool

Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req24_en1(&mut self, val: bool)

Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req25_en1(&self) -> bool

Writing a 1 to REQ25_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req25_en1(&mut self, val: bool)

Writing a 1 to REQ25_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req26_en1(&self) -> bool

Writing a 1 to REQ26_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req26_en1(&mut self, val: bool)

Writing a 1 to REQ26_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req27_en1(&self) -> bool

Writing a 1 to REQ27_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req27_en1(&mut self, val: bool)

Writing a 1 to REQ27_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req28_en1(&self) -> bool

Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req28_en1(&mut self, val: bool)

Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req29_en1(&self) -> bool

Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req29_en1(&mut self, val: bool)

Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req30_en1(&self) -> bool

Writing a 1 to REQ30_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req30_en1(&mut self, val: bool)

Writing a 1 to REQ30_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn req31_en1(&self) -> bool

Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

pub const fn set_req31_en1(&mut self, val: bool)

Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0.

Trait Implementations

impl Clone for Dma1ReqEnable0Clr

fn clone(&self) -> Dma1ReqEnable0Clr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dma1ReqEnable0Clr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Dma1ReqEnable0Clr

fn default() -> Dma1ReqEnable0Clr

Returns the “default value” for a type.

impl PartialEq for Dma1ReqEnable0Clr

fn eq(&self, other: &Dma1ReqEnable0Clr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dma1ReqEnable0Clr

impl Eq for Dma1ReqEnable0Clr

impl StructuralPartialEq for Dma1ReqEnable0Clr