Struct Dma1ReqEnable0 

#[repr(transparent)]
pub struct Dma1ReqEnable0(pub u32);

DMA1 Request Enable0

Tuple Fields

0: u32

Implementations

impl Dma1ReqEnable0

pub const fn req1_en1(&self) -> Req1En1

This register is used to enable and disable FLEXSPI0 receive event request.

pub const fn set_req1_en1(&mut self, val: Req1En1)

This register is used to enable and disable FLEXSPI0 receive event request.

pub const fn req2_en1(&self) -> Req2En1

This register is used to enable and disable FLEXSPI0 transmit event request.

pub const fn set_req2_en1(&mut self, val: Req2En1)

This register is used to enable and disable FLEXSPI0 transmit event request.

pub const fn req3_en1(&self) -> Req3En1

This register is used to enable and disable PINT0 INT0 request.

pub const fn set_req3_en1(&mut self, val: Req3En1)

This register is used to enable and disable PINT0 INT0 request.

pub const fn req4_en1(&self) -> Req4En1

This register is used to enable and disable PINT0 INT1 request.

pub const fn set_req4_en1(&mut self, val: Req4En1)

This register is used to enable and disable PINT0 INT1 request.

pub const fn req5_en1(&self) -> Req5En1

This register is used to enable and disable PINT0 INT2 request.

pub const fn set_req5_en1(&mut self, val: Req5En1)

This register is used to enable and disable PINT0 INT2 request.

pub const fn req6_en1(&self) -> Req6En1

This register is used to enable and disable PINT0 INT3 request.

pub const fn set_req6_en1(&mut self, val: Req6En1)

This register is used to enable and disable PINT0 INT3 request.

pub const fn req7_en1(&self) -> Req7En1

This register is used to enable and disable CTIMER0 DMAREQ_M0 request.

pub const fn set_req7_en1(&mut self, val: Req7En1)

This register is used to enable and disable CTIMER0 DMAREQ_M0 request.

pub const fn req8_en1(&self) -> Req8En1

This register is used to enable and disable CTIMER0 DMAREQ_M1 request.

pub const fn set_req8_en1(&mut self, val: Req8En1)

This register is used to enable and disable CTIMER0 DMAREQ_M1 request.

pub const fn req9_en1(&self) -> Req9En1

This register is used to enable and disable CTIMER1 DMAREQ_M0 request.

pub const fn set_req9_en1(&mut self, val: Req9En1)

This register is used to enable and disable CTIMER1 DMAREQ_M0 request.

pub const fn req10_en1(&self) -> Req10En1

This register is used to enable and disable CTIMER1 DMAREQ_M1 request.

pub const fn set_req10_en1(&mut self, val: Req10En1)

This register is used to enable and disable CTIMER1 DMAREQ_M1 request.

pub const fn req11_en1(&self) -> Req11En1

This register is used to enable and disable CTIMER2 DMAREQ_M0 request.

pub const fn set_req11_en1(&mut self, val: Req11En1)

This register is used to enable and disable CTIMER2 DMAREQ_M0 request.

pub const fn req12_en1(&self) -> Req12En1

This register is used to enable and disable CTIMER2 DMAREQ_M1 request.

pub const fn set_req12_en1(&mut self, val: Req12En1)

This register is used to enable and disable CTIMER2 DMAREQ_M1 request.

pub const fn req13_en1(&self) -> Req13En1

This register is used to enable and disable CTIMER3 DMAREQ_M0 request.

pub const fn set_req13_en1(&mut self, val: Req13En1)

This register is used to enable and disable CTIMER3 DMAREQ_M0 request.

pub const fn req14_en1(&self) -> Req14En1

This register is used to enable and disable CTIMER3 DMAREQ_M1 request.

pub const fn set_req14_en1(&mut self, val: Req14En1)

This register is used to enable and disable CTIMER3 DMAREQ_M1 request.

pub const fn req15_en1(&self) -> Req15En1

This register is used to enable and disable CTIMER4 DMAREQ_M0 request.

pub const fn set_req15_en1(&mut self, val: Req15En1)

This register is used to enable and disable CTIMER4 DMAREQ_M0 request.

pub const fn req16_en1(&self) -> Req16En1

This register is used to enable and disable CTIMER4 DMAREQ_M1 request.

pub const fn set_req16_en1(&mut self, val: Req16En1)

This register is used to enable and disable CTIMER4 DMAREQ_M1 request.

pub const fn req17_en1(&self) -> Req17En1

This register is used to enable and disable WUU0 wake up event request.

pub const fn set_req17_en1(&mut self, val: Req17En1)

This register is used to enable and disable WUU0 wake up event request.

pub const fn req18_en1(&self) -> Req18En1

This register is used to enable and disable MICFIL0 FIFO_request.

pub const fn set_req18_en1(&mut self, val: Req18En1)

This register is used to enable and disable MICFIL0 FIFO_request.

pub const fn req19_en1(&self) -> Req19En1

This register is used to enable and disable SCT0 DMA0 request.

pub const fn set_req19_en1(&mut self, val: Req19En1)

This register is used to enable and disable SCT0 DMA0 request.

pub const fn req20_en1(&self) -> Req20En1

This register is used to enable and disable SCT0 DMA1 request.

pub const fn set_req20_en1(&mut self, val: Req20En1)

This register is used to enable and disable SCT0 DMA1 request.

pub const fn req21_en1(&self) -> Req21En1

This register is used to enable and disable ADC0 FIFO A request.

pub const fn set_req21_en1(&mut self, val: Req21En1)

This register is used to enable and disable ADC0 FIFO A request.

pub const fn req22_en1(&self) -> Req22En1

This register is used to enable and disable ADC0 FIFO B request.

pub const fn set_req22_en1(&mut self, val: Req22En1)

This register is used to enable and disable ADC0 FIFO B request.

pub const fn req23_en1(&self) -> Req23En1

This register is used to enable and disable ADC1 FIFO A request.

pub const fn set_req23_en1(&mut self, val: Req23En1)

This register is used to enable and disable ADC1 FIFO A request.

pub const fn req24_en1(&self) -> Req24En1

This register is used to enable and disable ADC1 FIFO B request.

pub const fn set_req24_en1(&mut self, val: Req24En1)

This register is used to enable and disable ADC1 FIFO B request.

pub const fn req25_en1(&self) -> Req25En1

This register is used to enable and disable DAC0 FIFO_request.

pub const fn set_req25_en1(&mut self, val: Req25En1)

This register is used to enable and disable DAC0 FIFO_request.

pub const fn req26_en1(&self) -> Req26En1

This register is used to enable and disable DAC1 FIFO_request.

pub const fn set_req26_en1(&mut self, val: Req26En1)

This register is used to enable and disable DAC1 FIFO_request.

pub const fn req27_en1(&self) -> Req27En1

This register is used to enable and disable DAC2 FIFO_request.

pub const fn set_req27_en1(&mut self, val: Req27En1)

This register is used to enable and disable DAC2 FIFO_request.

pub const fn req28_en1(&self) -> Req28En1

This register is used to enable and disable CMP0 DMA_request.

pub const fn set_req28_en1(&mut self, val: Req28En1)

This register is used to enable and disable CMP0 DMA_request.

pub const fn req29_en1(&self) -> Req29En1

This register is used to enable and disable CMP1 DMA_request.

pub const fn set_req29_en1(&mut self, val: Req29En1)

This register is used to enable and disable CMP1 DMA_request.

pub const fn req30_en1(&self) -> Req30En1

This register is used to enable and disable CMP2 DMA_request.

pub const fn set_req30_en1(&mut self, val: Req30En1)

This register is used to enable and disable CMP2 DMA_request.

pub const fn req31_en1(&self) -> Req31En1

This register is used to enable and disable EVTG0 OUT0A request.

pub const fn set_req31_en1(&mut self, val: Req31En1)

This register is used to enable and disable EVTG0 OUT0A request.

Trait Implementations

impl Clone for Dma1ReqEnable0

fn clone(&self) -> Dma1ReqEnable0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dma1ReqEnable0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Dma1ReqEnable0

fn default() -> Dma1ReqEnable0

Returns the “default value” for a type.

impl PartialEq for Dma1ReqEnable0

fn eq(&self, other: &Dma1ReqEnable0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dma1ReqEnable0

impl Eq for Dma1ReqEnable0

impl StructuralPartialEq for Dma1ReqEnable0