#[repr(u8)]pub enum Sct0InmuxInp {
Show 128 variants
Val0 = 0,
Val1 = 1,
Val2 = 2,
Val3 = 3,
Val4 = 4,
Val5 = 5,
Val6 = 6,
Val7 = 7,
Val8 = 8,
Val9 = 9,
Val10 = 10,
Val11 = 11,
Val12 = 12,
Val13 = 13,
Val14 = 14,
Val15 = 15,
Val16 = 16,
Val17 = 17,
Val18 = 18,
Val19 = 19,
Val20 = 20,
Val21 = 21,
_RESERVED_16 = 22,
Val23 = 23,
Val24 = 24,
Val25 = 25,
Val26 = 26,
Val27 = 27,
Val28 = 28,
Val29 = 29,
Val30 = 30,
Val31 = 31,
Val32 = 32,
Val33 = 33,
Val34 = 34,
Val35 = 35,
Val36 = 36,
Val37 = 37,
Val38 = 38,
Val39 = 39,
Val40 = 40,
Val41 = 41,
Val42 = 42,
Val43 = 43,
Val44 = 44,
Val45 = 45,
Val46 = 46,
Val47 = 47,
Val48 = 48,
Val49 = 49,
Val50 = 50,
Val51 = 51,
Val52 = 52,
Val53 = 53,
Val54 = 54,
Val55 = 55,
Val56 = 56,
Val57 = 57,
_RESERVED_3a = 58,
_RESERVED_3b = 59,
Val60 = 60,
Val61 = 61,
Val62 = 62,
Val63 = 63,
Val64 = 64,
Val65 = 65,
Val66 = 66,
Val67 = 67,
Val68 = 68,
Val69 = 69,
Val70 = 70,
Val71 = 71,
Val72 = 72,
Val73 = 73,
Val74 = 74,
Val75 = 75,
Val76 = 76,
_RESERVED_4d = 77,
_RESERVED_4e = 78,
_RESERVED_4f = 79,
_RESERVED_50 = 80,
_RESERVED_51 = 81,
_RESERVED_52 = 82,
_RESERVED_53 = 83,
_RESERVED_54 = 84,
_RESERVED_55 = 85,
_RESERVED_56 = 86,
_RESERVED_57 = 87,
_RESERVED_58 = 88,
_RESERVED_59 = 89,
_RESERVED_5a = 90,
_RESERVED_5b = 91,
_RESERVED_5c = 92,
_RESERVED_5d = 93,
_RESERVED_5e = 94,
_RESERVED_5f = 95,
_RESERVED_60 = 96,
_RESERVED_61 = 97,
_RESERVED_62 = 98,
_RESERVED_63 = 99,
_RESERVED_64 = 100,
_RESERVED_65 = 101,
_RESERVED_66 = 102,
_RESERVED_67 = 103,
_RESERVED_68 = 104,
_RESERVED_69 = 105,
_RESERVED_6a = 106,
_RESERVED_6b = 107,
_RESERVED_6c = 108,
_RESERVED_6d = 109,
_RESERVED_6e = 110,
_RESERVED_6f = 111,
_RESERVED_70 = 112,
_RESERVED_71 = 113,
_RESERVED_72 = 114,
_RESERVED_73 = 115,
_RESERVED_74 = 116,
_RESERVED_75 = 117,
_RESERVED_76 = 118,
_RESERVED_77 = 119,
_RESERVED_78 = 120,
_RESERVED_79 = 121,
_RESERVED_7a = 122,
_RESERVED_7b = 123,
_RESERVED_7c = 124,
_RESERVED_7d = 125,
_RESERVED_7e = 126,
_RESERVED_7f = 127,
}Variants§
Val0 = 0
SCT0_IN0 input is selected.
Val1 = 1
SCT0_IN1 input is selected.
Val2 = 2
SCT0_IN2 input is selected.
Val3 = 3
SCT0_IN3 input is selected.
Val4 = 4
SCT0_IN4 input is selected.
Val5 = 5
SCT0_IN5 input is selected.
Val6 = 6
SCT0_IN6 input is selected.
Val7 = 7
SCT0_IN7 input is selected.
Val8 = 8
CTIMER0_MAT0 input is selected.
Val9 = 9
CTIMER1_MAT0 input is selected.
Val10 = 10
CTIMER2_MAT0 input is selected.
Val11 = 11
CTIMER3_MAT0 input is selected.
Val12 = 12
CTIMER4_MAT0 input is selected.
Val13 = 13
ADC0 ADC0_IRQ input is selected.
Val14 = 14
PINT GPIO_INT_BMAT input is selected.
Val15 = 15
usb0 start of frame input is selected.
Val16 = 16
usb1 start of frame input is selected.
Val17 = 17
SINC Filter CH0 Conversion Complete input is selected.
Val18 = 18
SINC Filter CH1 Conversion Complete input is selected.
Val19 = 19
SINC Filter CH2 Conversion Complete input is selected.
Val20 = 20
SINC Filter CH3 Conversion Complete input is selected.
Val21 = 21
SINC Filter CH4 Conversion Complete input is selected.
_RESERVED_16 = 22
Val23 = 23
DEBUG_HALTED input is selected.
Val24 = 24
ADC1_IRQ input is selected.
Val25 = 25
ADC0_tcomp[0] input is selected.
Val26 = 26
ADC0_tcomp[1] input is selected.
Val27 = 27
ADC0_tcomp[2] input is selected.
Val28 = 28
ADC0_tcomp[3] input is selected.
Val29 = 29
ADC1_tcomp[0] input is selected.
Val30 = 30
ADC1_tcomp[1] input is selected.
Val31 = 31
ADC1_tcomp[2] input is selected.
Val32 = 32
ADC1_tcomp[3] input is selected.
Val33 = 33
CMP0_OUT input is selected.
Val34 = 34
CMP1_OUT input is selected.
Val35 = 35
CMP2_OUT input is selected.
Val36 = 36
PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected.
Val37 = 37
PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected.
Val38 = 38
PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected.
Val39 = 39
PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected.
Val40 = 40
PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected.
Val41 = 41
PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected.
Val42 = 42
PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected.
Val43 = 43
PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected.
Val44 = 44
QDC0_CMP/POS_MATCH input is selected.
Val45 = 45
QDC1_CMP/POS_MATCH input is selected.
Val46 = 46
EVTG_OUT0A input is selected.
Val47 = 47
EVTG_OUT0B input is selected.
Val48 = 48
EVTG_OUT1A input is selected.
Val49 = 49
EVTG_OUT1B input is selected.
Val50 = 50
EVTG_OUT2A input is selected.
Val51 = 51
EVTG_OUT2B input is selected.
Val52 = 52
EVTG_OUT3A input is selected.
Val53 = 53
EVTG_OUT3B input is selected.
Val54 = 54
FC3_P0 (SDO, SDA) input is selected.
Val55 = 55
FC3_P1 (SCK, TXD, SCL) input is selected.
Val56 = 56
FC3_P2 (RTS, SCLS, TXD) input is selected.
Val57 = 57
FC3_P3 (PCS[0], CTS, SDAS) input is selected.
_RESERVED_3a = 58
_RESERVED_3b = 59
Val60 = 60
LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected.
Val61 = 61
LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected.
Val62 = 62
LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected.
Val63 = 63
LP_FLEXCOMM1 trig 0 input is selected.
Val64 = 64
LP_FLEXCOMM1 trig 1 input is selected.
Val65 = 65
LP_FLEXCOMM1 trig 2 input is selected.
Val66 = 66
LP_FLEXCOMM2 trig 0 input is selected.
Val67 = 67
LP_FLEXCOMM2 trig 1 input is selected.
Val68 = 68
LP_FLEXCOMM2 trig 2 input is selected.
Val69 = 69
LP_FLEXCOMM3 trig 0 input is selected.
Val70 = 70
LP_FLEXCOMM3 trig 1 input is selected.
Val71 = 71
LP_FLEXCOMM3 trig 2 input is selected.
Val72 = 72
LP_FLEXCOMM3 trig 3 input is selected.
Val73 = 73
SAI0 TX BCLK input is selected.
Val74 = 74
SAI0 RX BCLK input is selected.
Val75 = 75
SAI1 TX BCLK input is selected.
Val76 = 76
SAI1 RX BCLK input is selected.
_RESERVED_4d = 77
_RESERVED_4e = 78
_RESERVED_4f = 79
_RESERVED_50 = 80
_RESERVED_51 = 81
_RESERVED_52 = 82
_RESERVED_53 = 83
_RESERVED_54 = 84
_RESERVED_55 = 85
_RESERVED_56 = 86
_RESERVED_57 = 87
_RESERVED_58 = 88
_RESERVED_59 = 89
_RESERVED_5a = 90
_RESERVED_5b = 91
_RESERVED_5c = 92
_RESERVED_5d = 93
_RESERVED_5e = 94
_RESERVED_5f = 95
_RESERVED_60 = 96
_RESERVED_61 = 97
_RESERVED_62 = 98
_RESERVED_63 = 99
_RESERVED_64 = 100
_RESERVED_65 = 101
_RESERVED_66 = 102
_RESERVED_67 = 103
_RESERVED_68 = 104
_RESERVED_69 = 105
_RESERVED_6a = 106
_RESERVED_6b = 107
_RESERVED_6c = 108
_RESERVED_6d = 109
_RESERVED_6e = 110
_RESERVED_6f = 111
_RESERVED_70 = 112
_RESERVED_71 = 113
_RESERVED_72 = 114
_RESERVED_73 = 115
_RESERVED_74 = 116
_RESERVED_75 = 117
_RESERVED_76 = 118
_RESERVED_77 = 119
_RESERVED_78 = 120
_RESERVED_79 = 121
_RESERVED_7a = 122
_RESERVED_7b = 123
_RESERVED_7c = 124
_RESERVED_7d = 125
_RESERVED_7e = 126
_RESERVED_7f = 127
Implementations§
Source§impl Sct0InmuxInp
impl Sct0InmuxInp
Trait Implementations§
Source§impl Clone for Sct0InmuxInp
impl Clone for Sct0InmuxInp
Source§fn clone(&self) -> Sct0InmuxInp
fn clone(&self) -> Sct0InmuxInp
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more