Struct Syscon0 

pub struct Syscon0 { /* private fields */ }

SYSCON

Implementations

impl Syscon0

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn ahbmatprio(self) -> Reg<Ahbmatprio, RW>

AHB Matrix Priority Control

pub const fn cpu0stckcal(self) -> Reg<Cpu0stckcal, RW>

Secure CPU0 System Tick Calibration

pub const fn cpu0nstckcal(self) -> Reg<Cpu0nstckcal, RW>

Non-Secure CPU0 System Tick Calibration

pub const fn cpu1stckcal(self) -> Reg<Cpu1stckcal, RW>

System tick calibration for CPU1

pub const fn nmisrc(self) -> Reg<Nmisrc, RW>

NMI Source Select

pub const fn presetctrl0(self) -> Reg<Presetctrl0, RW>

Peripheral Reset Control 0

pub const fn presetctrl1(self) -> Reg<Presetctrl1, RW>

Peripheral Reset Control 1

pub const fn presetctrl2(self) -> Reg<Presetctrl2, RW>

Peripheral Reset Control 2

pub const fn presetctrl3(self) -> Reg<Presetctrl3, RW>

Peripheral Reset Control 3

pub const fn presetctrlset(self, n: usize) -> Reg<Presetctrlset, W>

Peripheral Reset Control Set

pub const fn presetctrlclr(self, n: usize) -> Reg<Presetctrlclr, W>

Peripheral Reset Control Clear

pub const fn ahbclkctrl0(self) -> Reg<Ahbclkctrl0, RW>

AHB Clock Control 0

pub const fn ahbclkctrl1(self) -> Reg<Ahbclkctrl1, RW>

AHB Clock Control 1

pub const fn ahbclkctrl2(self) -> Reg<Ahbclkctrl2, RW>

AHB Clock Control 2

pub const fn ahbclkctrl3(self) -> Reg<Ahbclkctrl3, RW>

AHB Clock Control 3

pub const fn ahbclkctrlset(self, n: usize) -> Reg<Ahbclkctrlset, W>

AHB Clock Control Set

pub const fn ahbclkctrlclr(self, n: usize) -> Reg<Ahbclkctrlclr, W>

AHB Clock Control Clear

pub const fn systickclksel0(self) -> Reg<Systickclksel0, RW>

CPU0 System Tick Timer Source Select

pub const fn systickclksel1(self) -> Reg<Systickclksel1, RW>

CPU1 System Tick Timer Source Select

pub const fn traceclksel(self) -> Reg<Traceclksel, RW>

Trace Clock Source Select

pub const fn ctimerclksel(self, n: usize) -> Reg<Ctimerclksel, RW>

CTIMER Clock Source Select

pub const fn clkoutsel(self) -> Reg<Clkoutsel, RW>

CLKOUT Clock Source Select

pub const fn adc0clksel(self) -> Reg<Adc0clksel, RW>

ADC0 Clock Source Select

pub const fn usb0clksel(self) -> Reg<Usb0clksel, RW>

USB-FS Clock Source Select

pub const fn fcclksel(self, n: usize) -> Reg<Fcclksel, RW>

LP_FLEXCOMM Clock Source Select for Fractional Rate Divider

pub const fn sctclksel(self) -> Reg<Sctclksel, RW>

SCTimer/PWM Clock Source Select

pub const fn systickclkdiv0(self) -> Reg<Systickclkdiv0, RW>

CPU0 System Tick Timer Divider

pub const fn systickclkdiv1(self) -> Reg<Systickclkdiv1, RW>

CPU1 System Tick Timer Divider

pub const fn traceclkdiv(self) -> Reg<Traceclkdiv, RW>

TRACE Clock Divider

pub const fn tsiclksel(self) -> Reg<Tsiclksel, RW>

TSI Function Clock Source Select

pub const fn sincfiltclksel(self) -> Reg<Sincfiltclksel, RW>

SINC FILTER Function Clock Source Select

pub const fn slowclkdiv(self) -> Reg<Slowclkdiv, RW>

SLOW_CLK Clock Divider

pub const fn tsiclkdiv(self) -> Reg<Tsiclkdiv, RW>

TSI Function Clock Divider

pub const fn ahbclkdiv(self) -> Reg<Ahbclkdiv, RW>

System Clock Divider

pub const fn clkoutdiv(self) -> Reg<Clkoutdiv, RW>

CLKOUT Clock Divider

pub const fn frohfdiv(self) -> Reg<Frohfdiv, RW>

FRO_HF_DIV Clock Divider

pub const fn wdt0clkdiv(self) -> Reg<Wdt0clkdiv, RW>

WDT0 Clock Divider

pub const fn adc0clkdiv(self) -> Reg<Adc0clkdiv, RW>

ADC0 Clock Divider

pub const fn usb0clkdiv(self) -> Reg<Usb0clkdiv, RW>

USB-FS Clock Divider

pub const fn sctclkdiv(self) -> Reg<Sctclkdiv, RW>

SCT/PWM Clock Divider

pub const fn pllclkdiv(self) -> Reg<Pllclkdiv, RW>

PLL Clock Divider

pub const fn ctimerclkdiv(self, n: usize) -> Reg<Ctimerclkdiv, RW>

CTimer Clock Divider

pub const fn pll1clk0div(self) -> Reg<Pll1clk0div, RW>

PLL1 Clock 0 Divider

pub const fn pll1clk1div(self) -> Reg<Pll1clk1div, RW>

PLL1 Clock 1 Divider

pub const fn utickclkdiv(self) -> Reg<Utickclkdiv, RW>

UTICK Clock Divider

pub const fn clkout_frgctrl(self) -> Reg<ClkoutFrgctrl, RW>

CLKOUT FRG Control

pub const fn clkunlock(self) -> Reg<Clkunlock, RW>

Clock Configuration Unlock

pub const fn nvm_ctrl(self) -> Reg<NvmCtrl, RW>

NVM Control

pub const fn romcr(self) -> Reg<Romcr, RW>

ROM Wait State

pub const fn smart_dmaint(self) -> Reg<SmartDmaint, RW>

SmartDMA Interrupt Hijack

pub const fn adc1clksel(self) -> Reg<Adc1clksel, RW>

ADC1 Clock Source Select

pub const fn adc1clkdiv(self) -> Reg<Adc1clkdiv, RW>

ADC1 Clock Divider

pub const fn ram_interleave(self) -> Reg<RamInterleave, RW>

Control PKC RAM Interleave Access

pub const fn dac0clksel(self) -> Reg<Dac0clksel, RW>

DAC0 Functional Clock Selection

pub const fn dac0clkdiv(self) -> Reg<Dac0clkdiv, RW>

DAC0 functional clock divider

pub const fn dac1clksel(self) -> Reg<Dac1clksel, RW>

DAC1 Functional Clock Selection

pub const fn dac1clkdiv(self) -> Reg<Dac1clkdiv, RW>

DAC1 functional clock divider

pub const fn dac2clksel(self) -> Reg<Dac2clksel, RW>

DAC2 Functional Clock Selection

pub const fn dac2clkdiv(self) -> Reg<Dac2clkdiv, RW>

DAC2 functional clock divider

pub const fn flex_spiclksel(self) -> Reg<FlexSpiclksel, RW>

FlexSPI Clock Selection

pub const fn flex_spiclkdiv(self) -> Reg<FlexSpiclkdiv, RW>

FlexSPI Clock Divider

pub const fn pllclkdivsel(self) -> Reg<Pllclkdivsel, RW>

PLL Clock Divider Clock Selection

pub const fn i3c0fclksel(self) -> Reg<I3c0fclksel, RW>

I3C0 Functional Clock Selection

pub const fn i3c0fclkstcsel(self) -> Reg<I3c0fclkstcsel, RW>

I3C0 FCLK_STC Clock Selection

pub const fn i3c0fclkstcdiv(self) -> Reg<I3c0fclkstcdiv, RW>

I3C0 FCLK_STC Clock Divider

pub const fn i3c0fclksdiv(self) -> Reg<I3c0fclksdiv, RW>

I3C0 FCLK Slow Clock Divider

pub const fn i3c0fclkdiv(self) -> Reg<I3c0fclkdiv, RW>

I3C0 Functional Clock FCLK Divider

pub const fn i3c0fclkssel(self) -> Reg<I3c0fclkssel, RW>

I3C0 FCLK Slow Selection

pub const fn micfilfclksel(self) -> Reg<Micfilfclksel, RW>

MICFIL Clock Selection

pub const fn micfilfclkdiv(self) -> Reg<Micfilfclkdiv, RW>

MICFIL Clock Division

pub const fn u_sdhcclksel(self) -> Reg<USdhcclksel, RW>

uSDHC Clock Selection

pub const fn u_sdhcclkdiv(self) -> Reg<USdhcclkdiv, RW>

uSDHC Function Clock Divider

pub const fn flexioclksel(self) -> Reg<Flexioclksel, RW>

FLEXIO Clock Selection

pub const fn flexioclkdiv(self) -> Reg<Flexioclkdiv, RW>

FLEXIO Function Clock Divider

pub const fn flexcan0clksel(self) -> Reg<Flexcan0clksel, RW>

FLEXCAN0 Clock Selection

pub const fn flexcan0clkdiv(self) -> Reg<Flexcan0clkdiv, RW>

FLEXCAN0 Function Clock Divider

pub const fn flexcan1clksel(self) -> Reg<Flexcan1clksel, RW>

FLEXCAN1 Clock Selection

pub const fn flexcan1clkdiv(self) -> Reg<Flexcan1clkdiv, RW>

FLEXCAN1 Function Clock Divider

pub const fn enetrmiiclksel(self) -> Reg<Enetrmiiclksel, RW>

Ethernet RMII Clock Selection

pub const fn enetrmiiclkdiv(self) -> Reg<Enetrmiiclkdiv, RW>

Ethernet RMII Function Clock Divider

pub const fn enetptprefclksel(self) -> Reg<Enetptprefclksel, RW>

Ethernet PTP REF Clock Selection

pub const fn enetptprefclkdiv(self) -> Reg<Enetptprefclkdiv, RW>

Ethernet PTP REF Function Clock Divider

pub const fn enet_phy_intf_sel(self) -> Reg<EnetPhyIntfSel, RW>

Ethernet PHY Interface Select

pub const fn enet_sbd_flow_ctrl(self) -> Reg<EnetSbdFlowCtrl, RW>

Sideband Flow Control

pub const fn ewm0clksel(self) -> Reg<Ewm0clksel, RW>

EWM0 Clock Selection

pub const fn wdt1clksel(self) -> Reg<Wdt1clksel, RW>

WDT1 Clock Selection

pub const fn wdt1clkdiv(self) -> Reg<Wdt1clkdiv, RW>

WDT1 Function Clock Divider

pub const fn ostimerclksel(self) -> Reg<Ostimerclksel, RW>

OSTIMER Clock Selection

pub const fn cmp0fclksel(self) -> Reg<Cmp0fclksel, RW>

CMP0 Function Clock Selection

pub const fn cmp0fclkdiv(self) -> Reg<Cmp0fclkdiv, RW>

CMP0 Function Clock Divider

pub const fn cmp0rrclksel(self) -> Reg<Cmp0rrclksel, RW>

CMP0 Round Robin Clock Selection

pub const fn cmp0rrclkdiv(self) -> Reg<Cmp0rrclkdiv, RW>

CMP0 Round Robin Clock Divider

pub const fn cmp1fclksel(self) -> Reg<Cmp1fclksel, RW>

CMP1 Function Clock Selection

pub const fn cmp1fclkdiv(self) -> Reg<Cmp1fclkdiv, RW>

CMP1 Function Clock Divider

pub const fn cmp1rrclksel(self) -> Reg<Cmp1rrclksel, RW>

CMP1 Round Robin Clock Source Select

pub const fn cmp1rrclkdiv(self) -> Reg<Cmp1rrclkdiv, RW>

CMP1 Round Robin Clock Division

pub const fn cmp2fclksel(self) -> Reg<Cmp2fclksel, RW>

CMP2 Function Clock Source Select

pub const fn cmp2fclkdiv(self) -> Reg<Cmp2fclkdiv, RW>

CMP2 Function Clock Division

pub const fn cmp2rrclksel(self) -> Reg<Cmp2rrclksel, RW>

CMP2 Round Robin Clock Source Select

pub const fn cmp2rrclkdiv(self) -> Reg<Cmp2rrclkdiv, RW>

CMP2 Round Robin Clock Division

pub const fn cpuctrl(self) -> Reg<Cpuctrl, RW>

CPU Control for Multiple Processors

pub const fn cpboot(self) -> Reg<Cpboot, RW>

Coprocessor Boot Address

pub const fn cpustat(self) -> Reg<Cpustat, R>

CPU Status

pub const fn lpcac_ctrl(self) -> Reg<LpcacCtrl, RW>

LPCAC Control

pub const fn flexcommclkdiv(self, n: usize) -> Reg<Flexcommclkdiv, RW>

LP_FLEXCOMM Clock Divider

pub const fn utickclksel(self) -> Reg<Utickclksel, RW>

UTICK Function Clock Source Select

pub const fn sai0clksel(self) -> Reg<Sai0clksel, RW>

SAI0 Function Clock Source Select

pub const fn sai1clksel(self) -> Reg<Sai1clksel, RW>

SAI1 Function Clock Source Select

pub const fn sai0clkdiv(self) -> Reg<Sai0clkdiv, RW>

SAI0 Function Clock Division

pub const fn sai1clkdiv(self) -> Reg<Sai1clkdiv, RW>

SAI1 Function Clock Division

pub const fn emvsim0clksel(self) -> Reg<Emvsim0clksel, RW>

EMVSIM0 Clock Source Select

pub const fn emvsim1clksel(self) -> Reg<Emvsim1clksel, RW>

EMVSIM1 Clock Source Select

pub const fn emvsim0clkdiv(self) -> Reg<Emvsim0clkdiv, RW>

EMVSIM0 Function Clock Division

pub const fn emvsim1clkdiv(self) -> Reg<Emvsim1clkdiv, RW>

EMVSIM1 Function Clock Division

pub const fn key_retain_ctrl(self) -> Reg<KeyRetainCtrl, RW>

Key Retain Control

pub const fn ref_clk_ctrl(self) -> Reg<RefClkCtrl, RW>

FRO 48MHz Reference Clock Control

pub const fn ref_clk_ctrl_set(self) -> Reg<RefClkCtrlSet, W>

FRO 48MHz Reference Clock Control Set

pub const fn ref_clk_ctrl_clr(self) -> Reg<RefClkCtrlClr, W>

FRO 48MHz Reference Clock Control Clear

pub const fn gdet_ctrl(self, n: usize) -> Reg<GdetCtrl, RW>

GDET Control Register

pub const fn els_asset_prot(self) -> Reg<ElsAssetProt, RW>

ELS Asset Protection Register

pub const fn els_lock_ctrl(self) -> Reg<ElsLockCtrl, RW>

ELS Lock Control

pub const fn els_lock_ctrl_dp(self) -> Reg<ElsLockCtrlDp, RW>

ELS Lock Control DP

pub const fn els_otp_lc_state(self) -> Reg<ElsOtpLcState, R>

Life Cycle State Register

pub const fn els_otp_lc_state_dp(self) -> Reg<ElsOtpLcStateDp, R>

Life Cycle State Register (Duplicate)

pub const fn els_temporal_state(self) -> Reg<ElsTemporalState, RW>

ELS Temporal State

pub const fn els_kdf_mask(self) -> Reg<ElsKdfMask, RW>

Key Derivation Function Mask

pub const fn els_as_cfg0(self) -> Reg<ElsAsCfg0, R>

ELS AS Configuration

pub const fn els_as_cfg1(self) -> Reg<ElsAsCfg1, R>

ELS AS Configuration1

pub const fn els_as_cfg2(self) -> Reg<ElsAsCfg2, R>

ELS AS Configuration2

pub const fn els_as_cfg3(self) -> Reg<ElsAsCfg3, R>

ELS AS Configuration3

pub const fn els_as_st0(self) -> Reg<ElsAsSt0, R>

ELS AS State Register

pub const fn els_as_st1(self) -> Reg<ElsAsSt1, R>

ELS AS State1

pub const fn els_as_boot_log0(self) -> Reg<ElsAsBootLog0, R>

Boot state captured during boot: Main ROM log

pub const fn els_as_boot_log1(self) -> Reg<ElsAsBootLog1, R>

Boot state captured during boot: Library log

pub const fn els_as_boot_log2(self) -> Reg<ElsAsBootLog2, R>

Boot state captured during boot: Hardware status signals log

pub const fn els_as_boot_log3(self) -> Reg<ElsAsBootLog3, R>

Boot state captured during boot: Security log

pub const fn els_as_flag0(self) -> Reg<ElsAsFlag0, R>

ELS AS Flag0

pub const fn els_as_flag1(self) -> Reg<ElsAsFlag1, R>

ELS AS Flag1

pub const fn clock_ctrl(self) -> Reg<ClockCtrl, RW>

Clock Control

pub const fn i3c1fclksel(self) -> Reg<I3c1fclksel, RW>

I3C1 Functional Clock Selection

pub const fn i3c1fclkstcsel(self) -> Reg<I3c1fclkstcsel, RW>

Selects the I3C1 Time Control clock

pub const fn i3c1fclkstcdiv(self) -> Reg<I3c1fclkstcdiv, RW>

I3C1 FCLK_STC Clock Divider

pub const fn i3c1fclksdiv(self) -> Reg<I3c1fclksdiv, RW>

I3C1 FCLK Slow clock Divider

pub const fn i3c1fclkdiv(self) -> Reg<I3c1fclkdiv, RW>

I3C1 Functional Clock FCLK Divider

pub const fn i3c1fclkssel(self) -> Reg<I3c1fclkssel, RW>

I3C1 FCLK Slow Selection

pub const fn etb_status(self) -> Reg<EtbStatus, RW>

ETB Counter Status Register

pub const fn etb_counter_ctrl(self) -> Reg<EtbCounterCtrl, RW>

ETB Counter Control Register

pub const fn etb_counter_reload(self) -> Reg<EtbCounterReload, RW>

ETB Counter Reload Register

pub const fn etb_counter_value(self) -> Reg<EtbCounterValue, R>

ETB Counter Value Register

pub const fn gray_code_lsb(self) -> Reg<GrayCodeLsb, RW>

Gray to Binary Converter Gray code_gray[31:0]

pub const fn gray_code_msb(self) -> Reg<GrayCodeMsb, RW>

Gray to Binary Converter Gray code_gray[41:32]

pub const fn binary_code_lsb(self) -> Reg<BinaryCodeLsb, R>

Gray to Binary Converter Binary Code [31:0]

pub const fn binary_code_msb(self) -> Reg<BinaryCodeMsb, R>

Gray to Binary Converter Binary Code [41:32]

pub const fn autoclkgateoverride(self) -> Reg<Autoclkgateoverride, RW>

Control Automatic Clock Gating

pub const fn autoclkgateoverridec(self) -> Reg<Autoclkgateoverridec, RW>

Control Automatic Clock Gating C

pub const fn pwm0subctl(self) -> Reg<Pwm0subctl, RW>

PWM0 Submodule Control

pub const fn pwm1subctl(self) -> Reg<Pwm1subctl, RW>

PWM1 Submodule Control

pub const fn ctimerglobalstarten(self) -> Reg<Ctimerglobalstarten, RW>

CTIMER Global Start Enable

pub const fn ecc_enable_ctrl(self) -> Reg<EccEnableCtrl, RW>

RAM ECC Enable Control

pub const fn debug_lock_en(self) -> Reg<DebugLockEn, RW>

Control Write Access to Security

pub const fn debug_features(self) -> Reg<DebugFeatures, RW>

Cortex Debug Features Control

pub const fn debug_features_dp(self) -> Reg<DebugFeaturesDp, RW>

Cortex Debug Features Control (Duplicate)

pub const fn swd_access_cpu0(self) -> Reg<SwdAccessCpu0, RW>

CPU0 Software Debug Access

pub const fn swd_access_cpu1(self) -> Reg<SwdAccessCpu1, W>

CPU1 Software Debug Access

pub const fn debug_auth_beacon(self) -> Reg<DebugAuthBeacon, RW>

Debug Authentication BEACON

pub const fn swd_access_dsp(self) -> Reg<SwdAccessDsp, RW>

DSP Software Debug Access

pub const fn jtag_id(self) -> Reg<JtagId, R>

JTAG Chip ID

pub const fn device_type(self) -> Reg<DeviceType, R>

Device Type

pub const fn device_id0(self) -> Reg<DeviceId0, R>

Device ID

pub const fn dieid(self) -> Reg<Dieid, R>

Chip Revision ID and Number

Trait Implementations

impl Clone for Syscon0

fn clone(&self) -> Syscon0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Syscon0

fn eq(&self, other: &Syscon0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Syscon0

impl Eq for Syscon0

impl Send for Syscon0

impl StructuralPartialEq for Syscon0

impl Sync for Syscon0