Enum RegCoreReg0Targ 

#[repr(u8)]
pub enum RegCoreReg0Targ {
    REG0_TARG_0 = 0,
    REG0_TARG_1 = 1,
    REG0_TARG_2 = 2,
    REG0_TARG_3 = 3,
    _RESERVED_4 = 4,
    _RESERVED_5 = 5,
    _RESERVED_6 = 6,
    _RESERVED_7 = 7,
    _RESERVED_8 = 8,
    _RESERVED_9 = 9,
    _RESERVED_a = 10,
    _RESERVED_b = 11,
    _RESERVED_c = 12,
    _RESERVED_d = 13,
    _RESERVED_e = 14,
    _RESERVED_f = 15,
    REG0_TARG_16 = 16,
    _RESERVED_11 = 17,
    _RESERVED_12 = 18,
    _RESERVED_13 = 19,
    _RESERVED_14 = 20,
    _RESERVED_15 = 21,
    _RESERVED_16 = 22,
    _RESERVED_17 = 23,
    _RESERVED_18 = 24,
    _RESERVED_19 = 25,
    _RESERVED_1a = 26,
    _RESERVED_1b = 27,
    _RESERVED_1c = 28,
    _RESERVED_1d = 29,
    REG0_TARG_30 = 30,
    REG0_TARG_31 = 31,
}

Variants

REG0_TARG_0 = 0

Power gated off.

REG0_TARG_1 = 1

Target core voltage = 0.725V.

REG0_TARG_2 = 2

Target core voltage = 0.750V.

REG0_TARG_3 = 3

Target core voltage = 0.775V.

_RESERVED_4 = 4

_RESERVED_5 = 5

_RESERVED_6 = 6

_RESERVED_7 = 7

_RESERVED_8 = 8

_RESERVED_9 = 9

_RESERVED_a = 10

_RESERVED_b = 11

_RESERVED_c = 12

_RESERVED_d = 13

_RESERVED_e = 14

_RESERVED_f = 15

REG0_TARG_16 = 16

Target core voltage = 1.100V.

_RESERVED_11 = 17

_RESERVED_12 = 18

_RESERVED_13 = 19

_RESERVED_14 = 20

_RESERVED_15 = 21

_RESERVED_16 = 22

_RESERVED_17 = 23

_RESERVED_18 = 24

_RESERVED_19 = 25

_RESERVED_1a = 26

_RESERVED_1b = 27

_RESERVED_1c = 28

_RESERVED_1d = 29

REG0_TARG_30 = 30

Target core voltage = 1.450V.

REG0_TARG_31 = 31

Power FET switched full on. No regulation.

Implementations

impl RegCoreReg0Targ

pub const fn from_bits(val: u8) -> RegCoreReg0Targ

pub const fn to_bits(self) -> u8

Trait Implementations

impl Clone for RegCoreReg0Targ

fn clone(&self) -> RegCoreReg0Targ

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RegCoreReg0Targ

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<RegCoreReg0Targ> for u8

fn from(val: RegCoreReg0Targ) -> u8

Converts to this type from the input type.

impl From<u8> for RegCoreReg0Targ

fn from(val: u8) -> RegCoreReg0Targ

Converts to this type from the input type.

impl Ord for RegCoreReg0Targ

fn cmp(&self, other: &RegCoreReg0Targ) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

impl PartialEq for RegCoreReg0Targ

fn eq(&self, other: &RegCoreReg0Targ) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for RegCoreReg0Targ

fn partial_cmp(&self, other: &RegCoreReg0Targ) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for RegCoreReg0Targ

impl Eq for RegCoreReg0Targ

impl StructuralPartialEq for RegCoreReg0Targ