Struct Ccgr0 

#[repr(transparent)]
pub struct Ccgr0(pub u32);

CCM Clock Gating Register 0

Tuple Fields

0: u32

Implementations

impl Ccgr0

pub const fn cg0(&self) -> u8

aips_tz1 clocks (aips_tz1_clk_enable)

pub const fn set_cg0(&mut self, val: u8)

aips_tz1 clocks (aips_tz1_clk_enable)

pub const fn cg1(&self) -> u8

aips_tz2 clocks (aips_tz2_clk_enable)

pub const fn set_cg1(&mut self, val: u8)

aips_tz2 clocks (aips_tz2_clk_enable)

pub const fn cg2(&self) -> u8

mqs clock ( mqs_hmclk_clock_enable)

pub const fn set_cg2(&mut self, val: u8)

mqs clock ( mqs_hmclk_clock_enable)

pub const fn cg3(&self) -> u8

Reserved

pub const fn set_cg3(&mut self, val: u8)

Reserved

pub const fn cg4(&self) -> u8

sim_m or sim_main register access clock (sim_m_mainclk_r_enable)

pub const fn set_cg4(&mut self, val: u8)

sim_m or sim_main register access clock (sim_m_mainclk_r_enable)

pub const fn cg5(&self) -> u8

dcp clock (dcp_clk_enable)

pub const fn set_cg5(&mut self, val: u8)

dcp clock (dcp_clk_enable)

pub const fn cg6(&self) -> u8

lpuart3 clock (lpuart3_clk_enable)

pub const fn set_cg6(&mut self, val: u8)

lpuart3 clock (lpuart3_clk_enable)

pub const fn cg7(&self) -> u8

can1 clock (can1_clk_enable)

pub const fn set_cg7(&mut self, val: u8)

can1 clock (can1_clk_enable)

pub const fn cg8(&self) -> u8

can1_serial clock (can1_serial_clk_enable)

pub const fn set_cg8(&mut self, val: u8)

can1_serial clock (can1_serial_clk_enable)

pub const fn cg9(&self) -> u8

can2 clock (can2_clk_enable)

pub const fn set_cg9(&mut self, val: u8)

can2 clock (can2_clk_enable)

pub const fn cg10(&self) -> u8

can2_serial clock (can2_serial_clk_enable)

pub const fn set_cg10(&mut self, val: u8)

can2_serial clock (can2_serial_clk_enable)

pub const fn cg11(&self) -> u8

trace clock (trace_clk_enable)

pub const fn set_cg11(&mut self, val: u8)

trace clock (trace_clk_enable)

pub const fn cg12(&self) -> u8

gpt2 bus clocks (gpt2_bus_clk_enable)

pub const fn set_cg12(&mut self, val: u8)

gpt2 bus clocks (gpt2_bus_clk_enable)

pub const fn cg13(&self) -> u8

gpt2 serial clocks (gpt2_serial_clk_enable)

pub const fn set_cg13(&mut self, val: u8)

gpt2 serial clocks (gpt2_serial_clk_enable)

pub const fn cg14(&self) -> u8

lpuart2 clock (lpuart2_clk_enable)

pub const fn set_cg14(&mut self, val: u8)

lpuart2 clock (lpuart2_clk_enable)

pub const fn cg15(&self) -> u8

gpio2_clocks (gpio2_clk_enable)

pub const fn set_cg15(&mut self, val: u8)

gpio2_clocks (gpio2_clk_enable)

Trait Implementations

impl Clone for Ccgr0

fn clone(&self) -> Ccgr0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ccgr0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Ccgr0

fn default() -> Ccgr0

Returns the “default value” for a type.

impl PartialEq for Ccgr0

fn eq(&self, other: &Ccgr0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ccgr0

impl Eq for Ccgr0

impl StructuralPartialEq for Ccgr0