Struct Ccgr5 

#[repr(transparent)]
pub struct Ccgr5(pub u32);

CCM Clock Gating Register 5

Tuple Fields

0: u32

Implementations

impl Ccgr5

pub const fn cg0(&self) -> u8

rom clock (rom_clk_enable)

pub const fn set_cg0(&mut self, val: u8)

rom clock (rom_clk_enable)

pub const fn cg1(&self) -> u8

flexio1 clock (flexio1_clk_enable)

pub const fn set_cg1(&mut self, val: u8)

flexio1 clock (flexio1_clk_enable)

pub const fn cg2(&self) -> u8

wdog3 clock (wdog3_clk_enable)

pub const fn set_cg2(&mut self, val: u8)

wdog3 clock (wdog3_clk_enable)

pub const fn cg3(&self) -> u8

dma clock (dma_clk_enable)

pub const fn set_cg3(&mut self, val: u8)

dma clock (dma_clk_enable)

pub const fn cg4(&self) -> u8

kpp clock (kpp_clk_enable)

pub const fn set_cg4(&mut self, val: u8)

kpp clock (kpp_clk_enable)

pub const fn cg5(&self) -> u8

wdog2 clock (wdog2_clk_enable)

pub const fn set_cg5(&mut self, val: u8)

wdog2 clock (wdog2_clk_enable)

pub const fn cg6(&self) -> u8

aipstz4 clocks (aips_tz4_clk_enable)

pub const fn set_cg6(&mut self, val: u8)

aipstz4 clocks (aips_tz4_clk_enable)

pub const fn cg7(&self) -> u8

spdif clock (spdif_clk_enable)

pub const fn set_cg7(&mut self, val: u8)

spdif clock (spdif_clk_enable)

pub const fn cg8(&self) -> u8

sim_main clock (sim_main_clk_enable)

pub const fn set_cg8(&mut self, val: u8)

sim_main clock (sim_main_clk_enable)

pub const fn cg9(&self) -> u8

sai1 clock (sai1_clk_enable)

pub const fn set_cg9(&mut self, val: u8)

sai1 clock (sai1_clk_enable)

pub const fn cg10(&self) -> u8

sai2 clock (sai2_clk_enable)

pub const fn set_cg10(&mut self, val: u8)

sai2 clock (sai2_clk_enable)

pub const fn cg11(&self) -> u8

sai3 clock (sai3_clk_enable)

pub const fn set_cg11(&mut self, val: u8)

sai3 clock (sai3_clk_enable)

pub const fn cg12(&self) -> u8

lpuart1 clock (lpuart1_clk_enable)

pub const fn set_cg12(&mut self, val: u8)

lpuart1 clock (lpuart1_clk_enable)

pub const fn cg13(&self) -> u8

lpuart7 clock (lpuart7_clk_enable)

pub const fn set_cg13(&mut self, val: u8)

lpuart7 clock (lpuart7_clk_enable)

pub const fn cg14(&self) -> u8

snvs_hp clock (snvs_hp_clk_enable)

pub const fn set_cg14(&mut self, val: u8)

snvs_hp clock (snvs_hp_clk_enable)

pub const fn cg15(&self) -> u8

snvs_lp clock (snvs_lp_clk_enable)

pub const fn set_cg15(&mut self, val: u8)

snvs_lp clock (snvs_lp_clk_enable)

Trait Implementations

impl Clone for Ccgr5

fn clone(&self) -> Ccgr5

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ccgr5

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Ccgr5

fn default() -> Ccgr5

Returns the “default value” for a type.

impl PartialEq for Ccgr5

fn eq(&self, other: &Ccgr5) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ccgr5

impl Eq for Ccgr5

impl StructuralPartialEq for Ccgr5