Module regs Copy item path Source AhbPeriph0SlaveRule0 Security access rules for AHB peripheral slaves area 0x40100000–0x4010FFFF AhbPeriph1SlaveRule0 the memory map is 0x40120000–0x40127FFF AhbPeriph2SlaveRule0 Security access rules for AHB peripheral slaves area 0x40140000–0x4014BFFF AhbPeriph3SlaveRule0 Security access rules for AHB peripheral slaves area 0x40150000–0x40158FFF AipsBridge0MemRule0 0x40110000–0x4011FFFF AipsBridge1MemRule0 Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there’re 16 sectors in total. AipsBridge1MemRule1 Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there’re 16 sectors in total. ApbGrp0MemRule0 Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total. ApbGrp0MemRule1 Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total. ApbGrp1MemRule0 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total. ApbGrp1MemRule1 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total. ApbGrp1MemRule2 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total. Cm33LockReg m33 lock control register Flexspi0Region0Rule FLEXSPI0 Region 0 Rule(n) Register Flexspi0Region1Rule0 FLEXSPI0 Region 1 Rule 0 Register Flexspi0Region2Rule0 FLEXSPI0 Region 2 Rule 0 Register Flexspi0Region3Rule0 FLEXSPI0 Region 3 Rule 0 Register Flexspi0Region4Rule0 FLEXSPI0 Region 4 Rule 0 Register MasterSecLevel master secure level register MasterSecLevelAntiPol master secure level anti-pole register MiscCtrlDpReg secure control duplicate register MiscCtrlReg secure control register PifHifi4XMemRule0 Security access rules for HiFi 4 memory sectors (0x24000000–0x240FFFFF). Each sector is 32 Kbytes, there’re 4 sectors in total. Ram00Rule SRAM Partition 00 Rule(n) Register Ram01Rule SRAM Partition 01 Rule(n) Register Ram02Rule SRAM Partition 02 Rule(n) Register Ram03Rule SRAM Partition 03 Rule(n) Register Ram04Rule SRAM Partition 04 Rule(n) Register Ram05Rule SRAM Partition 05 Rule(n) Register Ram06Rule SRAM Partition 06 Rule(n) Register Ram07Rule SRAM Partition 07 Rule(n) Register Ram08Rule SRAM Partition 08 Rule(n) Register Ram09Rule SRAM Partition 09 Rule(n) Register Ram10Rule SRAM Partition 10 Rule(n) Register Ram11Rule SRAM Partition 11 Rule(n) Register Ram12Rule SRAM Partition 12 Rule(n) Register Ram13Rule SRAM Partition 13 Rule(n) Register Ram14Rule SRAM Partition 14 Rule(n) Register Ram15Rule SRAM Partition 15 Rule(n) Register Ram16Rule SRAM Partition 16 Rule(n) Register Ram17Rule SRAM Partition 17 Rule(n) Register Ram18Rule SRAM Partition 18 Rule(n) Register Ram19Rule SRAM Partition 19 Rule(n) Register Ram20Rule SRAM Partition 20 Rule(n) Register Ram21Rule SRAM Partition 21 Rule(n) Register Ram22Rule SRAM Partition 22 Rule(n) Register Ram23Rule SRAM Partition 23 Rule(n) Register Ram24Rule SRAM Partition 24 Rule(n) Register Ram25Rule SRAM Partition 25 Rule(n) Register Ram26Rule SRAM Partition 26 Rule(n) Register Ram27Rule SRAM Partition 27 Rule(n) Register Ram28Rule SRAM Partition 28 Rule(n) Register Ram29Rule SRAM Partition 29 Rule(n) Register RomMemRule Memory ROM Rule(n) Register SecDspIntMask secure general purpose register 8 used to mask interrupts to DSP for security purpose SecGpioMask0 Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world. SecGpioMask1 Secure GPIO mask for port 1 pins. SecGpioMask2 Secure GPIO mask for port 2 pins. SecGpioMask3 Secure GPIO mask for port 3 pins. SecGpioMask4 Secure GPIO mask for port 4 pins. SecGpioMask5 Secure GPIO mask for port 5 pins. SecGpioMask6 Secure GPIO mask for port 6 pins. SecGpioMask7 Secure GPIO mask for port 7 pins. SecMaskLock sec_gp_reg write-lock bits SecVioAddr most recent security violation address for AHB layer n SecVioInfoValid security violation address/information registers valid flags SecVioMiscInfo most recent security violation miscellaneous information for AHB layer n SecurityCtrlMemRule0 0x40148000–0x4014BFFF