Struct SecGpioMask0 

#[repr(transparent)]
pub struct SecGpioMask0(pub u32);

Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world.

Tuple Fields

0: u32

Implementations

impl SecGpioMask0

pub const fn pio0_pin0_sec_mask(&self) -> bool

0 : Pin PIO0_0 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin0_sec_mask(&mut self, val: bool)

0 : Pin PIO0_0 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin1_sec_mask(&self) -> bool

0 : Pin PIO0_1 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin1_sec_mask(&mut self, val: bool)

0 : Pin PIO0_1 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin2_sec_mask(&self) -> bool

0 : Pin PIO0_2 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin2_sec_mask(&mut self, val: bool)

0 : Pin PIO0_2 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin3_sec_mask(&self) -> bool

0 : Pin PIO0_3 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin3_sec_mask(&mut self, val: bool)

0 : Pin PIO0_3 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin4_sec_mask(&self) -> bool

0 : Pin PIO0_4 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin4_sec_mask(&mut self, val: bool)

0 : Pin PIO0_4 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin5_sec_mask(&self) -> bool

0 : Pin PIO0_5 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin5_sec_mask(&mut self, val: bool)

0 : Pin PIO0_5 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin6_sec_mask(&self) -> bool

0 : Pin PIO0_6 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin6_sec_mask(&mut self, val: bool)

0 : Pin PIO0_6 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin7_sec_mask(&self) -> bool

0 : Pin PIO0_7 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin7_sec_mask(&mut self, val: bool)

0 : Pin PIO0_7 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin8_sec_mask(&self) -> bool

0 : Pin PIO0_8 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin8_sec_mask(&mut self, val: bool)

0 : Pin PIO0_8 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin9_sec_mask(&self) -> bool

0 : Pin PIO0_9 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin9_sec_mask(&mut self, val: bool)

0 : Pin PIO0_9 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin10_sec_mask(&self) -> bool

0 : Pin PIO0_10 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin10_sec_mask(&mut self, val: bool)

0 : Pin PIO0_10 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin11_sec_mask(&self) -> bool

0 : Pin PIO0_11 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin11_sec_mask(&mut self, val: bool)

0 : Pin PIO0_11 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin12_sec_mask(&self) -> bool

0 : Pin PIO0_12 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin12_sec_mask(&mut self, val: bool)

0 : Pin PIO0_12 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin13_sec_mask(&self) -> bool

0 : Pin PIO0_13 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin13_sec_mask(&mut self, val: bool)

0 : Pin PIO0_13 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin14_sec_mask(&self) -> bool

0 : Pin PIO0_14 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin14_sec_mask(&mut self, val: bool)

0 : Pin PIO0_14 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin15_sec_mask(&self) -> bool

0 : Pin PIO0_15 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin15_sec_mask(&mut self, val: bool)

0 : Pin PIO0_15 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin16_sec_mask(&self) -> bool

0 : Pin PIO0_16 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin16_sec_mask(&mut self, val: bool)

0 : Pin PIO0_16 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin17_sec_mask(&self) -> bool

0 : Pin PIO0_17 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin17_sec_mask(&mut self, val: bool)

0 : Pin PIO0_17 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin18_sec_mask(&self) -> bool

0 : Pin PIO0_18 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin18_sec_mask(&mut self, val: bool)

0 : Pin PIO0_18 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin19_sec_mask(&self) -> bool

0 : Pin PIO0_19 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin19_sec_mask(&mut self, val: bool)

0 : Pin PIO0_19 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin20_sec_mask(&self) -> bool

0 : Pin PIO0_20 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin20_sec_mask(&mut self, val: bool)

0 : Pin PIO0_20 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin21_sec_mask(&self) -> bool

0 : Pin PIO0_21 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin21_sec_mask(&mut self, val: bool)

0 : Pin PIO0_21 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin22_sec_mask(&self) -> bool

0 : Pin PIO0_22 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin22_sec_mask(&mut self, val: bool)

0 : Pin PIO0_22 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin23_sec_mask(&self) -> bool

0 : Pin PIO0_23 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin23_sec_mask(&mut self, val: bool)

0 : Pin PIO0_23 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin24_sec_mask(&self) -> bool

0 : Pin PIO0_24 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin24_sec_mask(&mut self, val: bool)

0 : Pin PIO0_24 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin25_sec_mask(&self) -> bool

0 : Pin PIO0_25 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin25_sec_mask(&mut self, val: bool)

0 : Pin PIO0_25 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin26_sec_mask(&self) -> bool

0 : Pin PIO0_26 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin26_sec_mask(&mut self, val: bool)

0 : Pin PIO0_26 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin27_sec_mask(&self) -> bool

0 : Pin PIO0_27 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin27_sec_mask(&mut self, val: bool)

0 : Pin PIO0_27 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin28_sec_mask(&self) -> bool

0 : Pin PIO0_28 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin28_sec_mask(&mut self, val: bool)

0 : Pin PIO0_28 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin29_sec_mask(&self) -> bool

0 : Pin PIO0_29 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin29_sec_mask(&mut self, val: bool)

0 : Pin PIO0_29 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin30_sec_mask(&self) -> bool

0 : Pin PIO0_30 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin30_sec_mask(&mut self, val: bool)

0 : Pin PIO0_30 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn pio0_pin31_sec_mask(&self) -> bool

0 : Pin PIO0_31 state is readable by non-secure world through non-secure GPIO port control registers

pub const fn set_pio0_pin31_sec_mask(&mut self, val: bool)

0 : Pin PIO0_31 state is readable by non-secure world through non-secure GPIO port control registers

Trait Implementations

impl Clone for SecGpioMask0

fn clone(&self) -> SecGpioMask0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for SecGpioMask0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for SecGpioMask0

fn default() -> SecGpioMask0

Returns the “default value” for a type.

impl PartialEq for SecGpioMask0

fn eq(&self, other: &SecGpioMask0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for SecGpioMask0

impl Eq for SecGpioMask0

impl StructuralPartialEq for SecGpioMask0