pub struct Espi { /* private fields */ }Expand description
a variant of SPI used by Intel to communicate with its processors via the PCH (aka Southbridge).
Implementations§
Source§impl Espi
impl Espi
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
Sourcepub const fn rambase(self) -> Reg<Rambase, RW>
pub const fn rambase(self) -> Reg<Rambase, RW>
Address of RAM to use for data. This tells the application where the RAM is located (up to 16K addressable).
Sourcepub const fn wirewo(self) -> Reg<Wirewo, RW>
pub const fn wirewo(self) -> Reg<Wirewo, RW>
Wire states for Host to see; if LPC, this is the IRQ states.
Sourcepub const fn stataddr(self) -> Reg<Stataddr, RW>
pub const fn stataddr(self) -> Reg<Stataddr, RW>
Location of Status block in memory space, if enabled.
Sourcepub const fn espimisc(self) -> Reg<Espimisc, RW>
pub const fn espimisc(self) -> Reg<Espimisc, RW>
Miscellaneous uses, such as Alert pin as GPIO (when not used for Alert).
Sourcepub const fn p0irule_stat(self) -> Reg<P0iruleStat, RW>
pub const fn p0irule_stat(self) -> Reg<P0iruleStat, RW>
The Port Set Interrupt-Rule and Set User Status register is used to set: The interrupt causes per port. That is, it is used to select what events from the port should cause an interrupt, if any. The user Status bits. The status byte returned to the host will be composed of both these user bits (which the application defines) and automatically generated status. The interrupt masks then are matched by sticky cause bits in PnSTAT (which can be read and then write-1 cleared). The sticky bits are set whether the interrupt is masked or not, but the masks cause an interrupt when the bits are set and the port is int enabled via INTENSET.
Sourcepub const fn p0addr(self) -> Reg<P0addr, RW>
pub const fn p0addr(self) -> Reg<P0addr, RW>
The Port Address register is used to set the mapped address in the LPC/eSPI memory space. For normal Ports, this is a 16-bit location in IO space or a 32-bit offset into PCIe address mapped space. It is not used for OOB, Bus Mastering, or Flash; see the PnOMFLEN register for those. For Endpoints, it is the base of a dword (64 bits). For Index/Data, it is the base of a word (32 bits). For mailbox memory, the address is modulus the length of the mailbox (x2 for both directions). So, if a 16-byte mailbox (single), the offset must have bits 3:0 set to 0 (that is &~0xF). If split directions, then normally bits 4:0 would be set to 0 (that is &~0x1F).
Sourcepub const fn p0omflen(self) -> Reg<P0omflen, RW>
pub const fn p0omflen(self) -> Reg<P0omflen, RW>
The Port OOB, Mastering, Flash length is used for OOB to Host and Bus Mastering and Flash to or from Host. The PnADDR register is not used for either OOB or Bus Mastering. Instead, this register (in same location) is written with byte length message (including address for Mastering and Flash) along with direction. Writing to the SSTCL field of the PIRuleState will notify the Host to perform the transaction. Clearing it before the Host has started a transaction will cancel it, but only if it has not yet seen the Status.
Sourcepub const fn p0data_out(self) -> Reg<P0dataOut, RW>
pub const fn p0data_out(self) -> Reg<P0dataOut, RW>
no description available
Sourcepub const fn p1irule_stat(self) -> Reg<P1iruleStat, RW>
pub const fn p1irule_stat(self) -> Reg<P1iruleStat, RW>
The Port Set Interrupt-Rule and Set User Status register is used to set: The interrupt causes per port. That is, it is used to select what events from the port should cause an interrupt, if any. The user Status bits. The status byte returned to the host will be composed of both these user bits (which the application defines) and automatically generated status. The interrupt masks then are matched by sticky cause bits in PnSTAT (which can be read and then write-1 cleared). The sticky bits are set whether the interrupt is masked or not, but the masks cause an interrupt when the bits are set and the port is int enabled via INTENSET.
Sourcepub const fn p1addr(self) -> Reg<P1addr, RW>
pub const fn p1addr(self) -> Reg<P1addr, RW>
The Port Address register is used to set the mapped address in the LPC/eSPI memory space. For normal Ports, this is a 16-bit location in IO space or a 32-bit offset into PCIe address mapped space. It is not used for OOB, Bus Mastering, or Flash; see the PnOMFLEN register for those. For Endpoints, it is the base of a dword (64 bits). For Index/Data, it is the base of a word (32 bits). For mailbox memory, the address is modulus the length of the mailbox (x2 for both directions). So, if a 16-byte mailbox (single), the offset must have bits 3:0 set to 0 (that is &~0xF). If split directions, then normally bits 4:0 would be set to 0 (that is &~0x1F).
Sourcepub const fn p1omflen(self) -> Reg<P1omflen, RW>
pub const fn p1omflen(self) -> Reg<P1omflen, RW>
The Port OOB, Mastering, Flash length is used for OOB to Host and Bus Mastering and Flash to or from Host. The PnADDR register is not used for either OOB or Bus Mastering. Instead, this register (in same location) is written with byte length message (including address for Mastering and Flash) along with direction. Writing to the SSTCL field of the PIRuleState will notify the Host to perform the transaction. Clearing it before the Host has started a transaction will cancel it, but only if it has not yet seen the Status.
Sourcepub const fn p1data_out(self) -> Reg<P1dataOut, RW>
pub const fn p1data_out(self) -> Reg<P1dataOut, RW>
no description available
Sourcepub const fn p2irule_stat(self) -> Reg<P2iruleStat, RW>
pub const fn p2irule_stat(self) -> Reg<P2iruleStat, RW>
The Port Set Interrupt-Rule and Set User Status register is used to set: The interrupt causes per port. That is, it is used to select what events from the port should cause an interrupt, if any. The user Status bits. The status byte returned to the host will be composed of both these user bits (which the application defines) and automatically generated status. The interrupt masks then are matched by sticky cause bits in PnSTAT (which can be read and then write-1 cleared). The sticky bits are set whether the interrupt is masked or not, but the masks cause an interrupt when the bits are set and the port is int enabled via INTENSET.
Sourcepub const fn p2addr(self) -> Reg<P2addr, RW>
pub const fn p2addr(self) -> Reg<P2addr, RW>
The Port Address register is used to set the mapped address in the LPC/eSPI memory space. For normal Ports, this is a 16-bit location in IO space or a 32-bit offset into PCIe address mapped space. It is not used for OOB, Bus Mastering, or Flash; see the PnOMFLEN register for those. For Endpoints, it is the base of a dword (64 bits). For Index/Data, it is the base of a word (32 bits). For mailbox memory, the address is modulus the length of the mailbox (x2 for both directions). So, if a 16-byte mailbox (single), the offset must have bits 3:0 set to 0 (that is &~0xF). If split directions, then normally bits 4:0 would be set to 0 (that is &~0x1F).
Sourcepub const fn p2omflen(self) -> Reg<P2omflen, RW>
pub const fn p2omflen(self) -> Reg<P2omflen, RW>
The Port OOB, Mastering, Flash length is used for OOB to Host and Bus Mastering and Flash to or from Host. The PnADDR register is not used for either OOB or Bus Mastering. Instead, this register (in same location) is written with byte length message (including address for Mastering and Flash) along with direction. Writing to the SSTCL field of the PIRuleState will notify the Host to perform the transaction. Clearing it before the Host has started a transaction will cancel it, but only if it has not yet seen the Status.
Sourcepub const fn p2data_out(self) -> Reg<P2dataOut, RW>
pub const fn p2data_out(self) -> Reg<P2dataOut, RW>
no description available
Sourcepub const fn p3irule_stat(self) -> Reg<P3iruleStat, RW>
pub const fn p3irule_stat(self) -> Reg<P3iruleStat, RW>
The Port Set Interrupt-Rule and Set User Status register is used to set: The interrupt causes per port. That is, it is used to select what events from the port should cause an interrupt, if any. The user Status bits. The status byte returned to the host will be composed of both these user bits (which the application defines) and automatically generated status. The interrupt masks then are matched by sticky cause bits in PnSTAT (which can be read and then write-1 cleared). The sticky bits are set whether the interrupt is masked or not, but the masks cause an interrupt when the bits are set and the port is int enabled via INTENSET.
Sourcepub const fn p3addr(self) -> Reg<P3addr, RW>
pub const fn p3addr(self) -> Reg<P3addr, RW>
The Port Address register is used to set the mapped address in the LPC/eSPI memory space. For normal Ports, this is a 16-bit location in IO space or a 32-bit offset into PCIe address mapped space. It is not used for OOB, Bus Mastering, or Flash; see the PnOMFLEN register for those. For Endpoints, it is the base of a dword (64 bits). For Index/Data, it is the base of a word (32 bits). For mailbox memory, the address is modulus the length of the mailbox (x2 for both directions). So, if a 16-byte mailbox (single), the offset must have bits 3:0 set to 0 (that is &~0xF). If split directions, then normally bits 4:0 would be set to 0 (that is &~0x1F).
Sourcepub const fn p3omflen(self) -> Reg<P3omflen, RW>
pub const fn p3omflen(self) -> Reg<P3omflen, RW>
The Port OOB, Mastering, Flash length is used for OOB to Host and Bus Mastering and Flash to or from Host. The PnADDR register is not used for either OOB or Bus Mastering. Instead, this register (in same location) is written with byte length message (including address for Mastering and Flash) along with direction. Writing to the SSTCL field of the PIRuleState will notify the Host to perform the transaction. Clearing it before the Host has started a transaction will cancel it, but only if it has not yet seen the Status.
Sourcepub const fn p3data_out(self) -> Reg<P3dataOut, RW>
pub const fn p3data_out(self) -> Reg<P3dataOut, RW>
no description available
Sourcepub const fn p4irule_stat(self) -> Reg<P4iruleStat, RW>
pub const fn p4irule_stat(self) -> Reg<P4iruleStat, RW>
The Port Set Interrupt-Rule and Set User Status register is used to set: The interrupt causes per port. That is, it is used to select what events from the port should cause an interrupt, if any. The user Status bits. The status byte returned to the host will be composed of both these user bits (which the application defines) and automatically generated status. The interrupt masks then are matched by sticky cause bits in PnSTAT (which can be read and then write-1 cleared). The sticky bits are set whether the interrupt is masked or not, but the masks cause an interrupt when the bits are set and the port is int enabled via INTENSET.
Sourcepub const fn p4addr(self) -> Reg<P4addr, RW>
pub const fn p4addr(self) -> Reg<P4addr, RW>
The Port Address register is used to set the mapped address in the LPC/eSPI memory space. For normal Ports, this is a 16-bit location in IO space or a 32-bit offset into PCIe address mapped space. It is not used for OOB, Bus Mastering, or Flash; see the PnOMFLEN register for those. For Endpoints, it is the base of a dword (64 bits). For Index/Data, it is the base of a word (32 bits). For mailbox memory, the address is modulus the length of the mailbox (x2 for both directions). So, if a 16-byte mailbox (single), the offset must have bits 3:0 set to 0 (that is &~0xF). If split directions, then normally bits 4:0 would be set to 0 (that is &~0x1F).
Sourcepub const fn p4omflen(self) -> Reg<P4omflen, RW>
pub const fn p4omflen(self) -> Reg<P4omflen, RW>
The Port OOB, Mastering, Flash length is used for OOB to Host and Bus Mastering and Flash to or from Host. The PnADDR register is not used for either OOB or Bus Mastering. Instead, this register (in same location) is written with byte length message (including address for Mastering and Flash) along with direction. Writing to the SSTCL field of the PIRuleState will notify the Host to perform the transaction. Clearing it before the Host has started a transaction will cancel it, but only if it has not yet seen the Status.
Sourcepub const fn p4data_out(self) -> Reg<P4dataOut, RW>
pub const fn p4data_out(self) -> Reg<P4dataOut, RW>
no description available