pub struct Interp { /* private fields */ }
Implementations§
source§impl Interp
impl Interp
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
sourcepub const fn pop_lane0(self) -> Reg<u32, RW>
pub const fn pop_lane0(self) -> Reg<u32, RW>
Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
sourcepub const fn pop_lane1(self) -> Reg<u32, RW>
pub const fn pop_lane1(self) -> Reg<u32, RW>
Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
sourcepub const fn pop_full(self) -> Reg<u32, RW>
pub const fn pop_full(self) -> Reg<u32, RW>
Read FULL result, and simultaneously write lane results to both accumulators (POP).
sourcepub const fn peek_lane0(self) -> Reg<u32, RW>
pub const fn peek_lane0(self) -> Reg<u32, RW>
Read LANE0 result, without altering any internal state (PEEK).
sourcepub const fn peek_lane1(self) -> Reg<u32, RW>
pub const fn peek_lane1(self) -> Reg<u32, RW>
Read LANE1 result, without altering any internal state (PEEK).
sourcepub const fn peek_full(self) -> Reg<u32, RW>
pub const fn peek_full(self) -> Reg<u32, RW>
Read FULL result, without altering any internal state (PEEK).
sourcepub const fn ctrl_lane0(self) -> Reg<Interp1ctrlLane0, RW>
pub const fn ctrl_lane0(self) -> Reg<Interp1ctrlLane0, RW>
Control register for lane 0
sourcepub const fn ctrl_lane1(self) -> Reg<Interp1ctrlLane1, RW>
pub const fn ctrl_lane1(self) -> Reg<Interp1ctrlLane1, RW>
Control register for lane 1
sourcepub const fn accum0_add(self) -> Reg<Interp1accum0add, RW>
pub const fn accum0_add(self) -> Reg<Interp1accum0add, RW>
Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added).
sourcepub const fn accum1_add(self) -> Reg<Interp1accum1add, RW>
pub const fn accum1_add(self) -> Reg<Interp1accum1add, RW>
Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added).
sourcepub const fn base_1and0(self) -> Reg<u32, RW>
pub const fn base_1and0(self) -> Reg<u32, RW>
On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
Trait Implementations§
impl Copy for Interp
impl Eq for Interp
impl Send for Interp
impl StructuralPartialEq for Interp
impl Sync for Interp
Auto Trait Implementations§
impl Freeze for Interp
impl RefUnwindSafe for Interp
impl Unpin for Interp
impl UnwindSafe for Interp
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)