#[repr(transparent)]pub struct Wdsel(pub u32);
Expand description
Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it’s recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect.
Tuple Fields§
§0: u32
Implementations§
Source§impl Wdsel
impl Wdsel
Sourcepub const fn reset_powman_async(&self) -> bool
pub const fn reset_powman_async(&self) -> bool
If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running
Sourcepub fn set_reset_powman_async(&mut self, val: bool)
pub fn set_reset_powman_async(&mut self, val: bool)
If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running
Sourcepub const fn reset_powman(&self) -> bool
pub const fn reset_powman(&self) -> bool
If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true
Sourcepub fn set_reset_powman(&mut self, val: bool)
pub fn set_reset_powman(&mut self, val: bool)
If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true
Sourcepub const fn reset_swcore(&self) -> bool
pub const fn reset_swcore(&self) -> bool
If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain
Sourcepub fn set_reset_swcore(&mut self, val: bool)
pub fn set_reset_swcore(&mut self, val: bool)
If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain
Sourcepub const fn reset_rsm(&self) -> bool
pub const fn reset_rsm(&self) -> bool
If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector
Sourcepub fn set_reset_rsm(&mut self, val: bool)
pub fn set_reset_rsm(&mut self, val: bool)
If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector