Module typelevel

Type-level interrupt infrastructure.

This module contains one type per interrupt. This is used for checking at compile time that the interrupts are correctly bound to HAL drivers.

As an end user, you shouldn’t need to use this module directly. Use the crate::bind_interrupts! macro to bind interrupts, and the [crate::interrupt] module to manually register interrupt handlers and manipulate interrupts directly (pending/unpending, enabling/disabling, setting the priority, etc…)

Enums

• ADC
  ADC typelevel interrupt.
• CAN1_RX0
  CAN1_RX0 typelevel interrupt.
• CAN1_RX1
  CAN1_RX1 typelevel interrupt.
• CAN1_SCE
  CAN1_SCE typelevel interrupt.
• CAN1_TX
  CAN1_TX typelevel interrupt.
• CAN2_RX0
  CAN2_RX0 typelevel interrupt.
• CAN2_RX1
  CAN2_RX1 typelevel interrupt.
• CAN2_SCE
  CAN2_SCE typelevel interrupt.
• CAN2_TX
  CAN2_TX typelevel interrupt.
• CRYP
  CRYP typelevel interrupt.
• DMA1_STREAM0
  DMA1_STREAM0 typelevel interrupt.
• DMA1_STREAM1
  DMA1_STREAM1 typelevel interrupt.
• DMA1_STREAM2
  DMA1_STREAM2 typelevel interrupt.
• DMA1_STREAM3
  DMA1_STREAM3 typelevel interrupt.
• DMA1_STREAM4
  DMA1_STREAM4 typelevel interrupt.
• DMA1_STREAM5
  DMA1_STREAM5 typelevel interrupt.
• DMA1_STREAM6
  DMA1_STREAM6 typelevel interrupt.
• DMA1_STREAM7
  DMA1_STREAM7 typelevel interrupt.
• DMA2_STREAM0
  DMA2_STREAM0 typelevel interrupt.
• DMA2_STREAM1
  DMA2_STREAM1 typelevel interrupt.
• DMA2_STREAM2
  DMA2_STREAM2 typelevel interrupt.
• DMA2_STREAM3
  DMA2_STREAM3 typelevel interrupt.
• DMA2_STREAM4
  DMA2_STREAM4 typelevel interrupt.
• DMA2_STREAM5
  DMA2_STREAM5 typelevel interrupt.
• DMA2_STREAM6
  DMA2_STREAM6 typelevel interrupt.
• DMA2_STREAM7
  DMA2_STREAM7 typelevel interrupt.
• EXTI0
  EXTI0 typelevel interrupt.
• EXTI1
  EXTI1 typelevel interrupt.
• EXTI2
  EXTI2 typelevel interrupt.
• EXTI3
  EXTI3 typelevel interrupt.
• EXTI4
  EXTI4 typelevel interrupt.
• EXTI9_5
  EXTI9_5 typelevel interrupt.
• EXTI15_10
  EXTI15_10 typelevel interrupt.
• FLASH
  FLASH typelevel interrupt.
• FPU
  FPU typelevel interrupt.
• FSMC
  FSMC typelevel interrupt.
• HASH_RNG
  HASH_RNG typelevel interrupt.
• I2C1_ER
  I2C1_ER typelevel interrupt.
• I2C1_EV
  I2C1_EV typelevel interrupt.
• I2C2_ER
  I2C2_ER typelevel interrupt.
• I2C2_EV
  I2C2_EV typelevel interrupt.
• I2C3_ER
  I2C3_ER typelevel interrupt.
• I2C3_EV
  I2C3_EV typelevel interrupt.
• OTG_FS
  OTG_FS typelevel interrupt.
• OTG_FS_WKUP
  OTG_FS_WKUP typelevel interrupt.
• OTG_HS
  OTG_HS typelevel interrupt.
• OTG_HS_EP1_IN
  OTG_HS_EP1_IN typelevel interrupt.
• OTG_HS_EP1_OUT
  OTG_HS_EP1_OUT typelevel interrupt.
• OTG_HS_WKUP
  OTG_HS_WKUP typelevel interrupt.
• PVD
  PVD typelevel interrupt.
• RCC
  RCC typelevel interrupt.
• RTC_ALARM
  RTC_ALARM typelevel interrupt.
• RTC_WKUP
  RTC_WKUP typelevel interrupt.
• SDIO
  SDIO typelevel interrupt.
• SPI1
  SPI1 typelevel interrupt.
• SPI2
  SPI2 typelevel interrupt.
• SPI3
  SPI3 typelevel interrupt.
• TAMP_STAMP
  TAMP_STAMP typelevel interrupt.
• TIM2
  TIM2 typelevel interrupt.
• TIM3
  TIM3 typelevel interrupt.
• TIM4
  TIM4 typelevel interrupt.
• TIM5
  TIM5 typelevel interrupt.
• TIM7
  TIM7 typelevel interrupt.
• TIM1_BRK_TIM9
  TIM1_BRK_TIM9 typelevel interrupt.
• TIM1_CC
  TIM1_CC typelevel interrupt.
• TIM1_TRG_COM_TIM11
  TIM1_TRG_COM_TIM11 typelevel interrupt.
• TIM1_UP_TIM10
  TIM1_UP_TIM10 typelevel interrupt.
• TIM6_DAC
  TIM6_DAC typelevel interrupt.
• TIM8_BRK_TIM12
  TIM8_BRK_TIM12 typelevel interrupt.
• TIM8_CC
  TIM8_CC typelevel interrupt.
• TIM8_TRG_COM_TIM14
  TIM8_TRG_COM_TIM14 typelevel interrupt.
• TIM8_UP_TIM13
  TIM8_UP_TIM13 typelevel interrupt.
• UART4
  UART4 typelevel interrupt.
• UART5
  UART5 typelevel interrupt.
• USART1
  USART1 typelevel interrupt.
• USART2
  USART2 typelevel interrupt.
• USART3
  USART3 typelevel interrupt.
• USART6
  USART6 typelevel interrupt.
• WWDG
  WWDG typelevel interrupt.

Traits

• Binding
  Compile-time assertion that an interrupt has been bound to a handler.
• Handler
  Interrupt handler trait.
• Interrupt
  Type-level interrupt.