Module types 

Type-system: sealed and capability markers, channel markers, pin-presence (PinSet) and channel-config tokens, indexed channel types and trigger types.

Structs

DataClk

Transceiver has a DATIN and a CKIN pin.

DataOnly

Transceiver has a DATIN pin, no CKIN (clock from CKOUT or the neighbor).

DatinCfg

Pin token: the transceiver gets a DATIN pin (AF already configured). Only accepted by the configure_pins slot belonging to M’s transceiver.

DckCfg

Pin token: the transceiver gets DATIN + CKIN.

Disabled

Powered down

Enabled

Powered up

Flt0

DFSDM filter marker 0.

Flt1

DFSDM filter marker 1.

Flt2

DFSDM filter marker 2.

Flt3

DFSDM filter marker 3.

Flt4

DFSDM filter marker 4.

Flt5

DFSDM filter marker 5.

Flt6

DFSDM filter marker 6.

Flt7

DFSDM filter marker 7.

Hwid

Snapshot of the DFSDM version/ID register cluster @0x7F0 (RM0475 29.9 / RM0436/RM0441/RM0442). Present only on instances whose silicon carries the HWID cluster; see capability::HasHwid.

InjDma

Injected-conversion DMA.

ManchesterMode

Manchester-coded input, clock recovered from the data line (SITP = 2/3).

NeighborPins

CHINSEL = 1, pins live on M::Next’s slot

NoDma

No DMA.

NoPins

Transceiver has no own pins (unused, parallel input, or borrowing the neighbor’s).

NoPinsCfg

Pin token: the transceiver gets no pins. Valid in any slot.

OutputDisabled

Clock output disabled

OutputEnabled

Clock output enabled

OwnPins

CHINSEL = 0

ParallelAdcMode

16-bit parallel input from ADC writes (DATMPX = 1).

ParallelInterleaved

16-bit parallel input from CPU/DMA writes (DATMPX = 2), Interleaved packing (DATPACK = 1).

ParallelPaired

16-bit parallel input in a dual pair: the even channel uses Dual packing (DATPACK = 2), the odd channel is auto-fed from it.

ParallelStandard

16-bit parallel input from CPU/DMA writes (DATMPX = 2), Standard packing (DATPACK = 0).

RegDma

Regular-conversion DMA.

SpiCkoutMode

SPI input, clock derived from CKOUT (SPICKSEL = 1..3).

SpiExtMode

SPI input, clock from own CKIN pin (SPICKSEL = 0).

Tcv0

DFSDM transceiver marker 0.

Tcv1

DFSDM transceiver marker 1.

Tcv2

DFSDM transceiver marker 2.

Tcv3

DFSDM transceiver marker 3.

Tcv4

DFSDM transceiver marker 4.

Tcv5

DFSDM transceiver marker 5.

Tcv6

DFSDM transceiver marker 6.

Tcv7

DFSDM transceiver marker 7.

Enums

FilterChannel

DFSDM filter identifier.

InjectedTrigger

Injected-conversion trigger selection for a filter.

TransceiverChannel

DFSDM transceiver identifier.

Traits

ChannelCfg

Accepted by one configure_pins slot. Presence is the type-level pin state that flows into the split.

ChannelMode

Operational mode of a built Transceiver. Determined by which builder constructor was used; encodes the SITP/SPICKSEL/DATMPX semantics.

Ckin0Pin

Ckin0Pin pin trait

Ckin1Pin

Ckin1Pin pin trait

Ckin2Pin

Ckin2Pin pin trait

Ckin3Pin

Ckin3Pin pin trait

Ckin4Pin

Ckin4Pin pin trait

Ckin5Pin

Ckin5Pin pin trait

Ckin6Pin

Ckin6Pin pin trait

Ckin7Pin

Ckin7Pin pin trait

CkinPin

Associates a DFSDM clock-input pin with a transceiver.

CkoutPin

CkoutPin pin trait

ClockOutputMode

Marker trait for clock-output modes.

Datin0Pin

Datin0Pin pin trait

Datin1Pin

Datin1Pin pin trait

Datin2Pin

Datin2Pin pin trait

Datin3Pin

Datin3Pin pin trait

Datin4Pin

Datin4Pin pin trait

Datin5Pin

Datin5Pin pin trait

Datin6Pin

Datin6Pin pin trait

Datin7Pin

Datin7Pin pin trait

DatinPin

Associates a DFSDM data-input pin with a transceiver.

Dma

Dma DMA request trait

DmaMode

DMA mode of a filter half.

DualPackingAllowed

Marks transceivers allowed to use dual data-packing mode.

ExternalSerialMode

Marker for serial modes relying on an external clock; gates clock-absence-detection sync.

FilterDma

DMA half of a filter, erased over the concrete half type.

FilterMarker

HasData

Pin sets that include a DATIN pin.

HasDataAndClk

Pin sets that include a DATIN and a CKIN pin.

Instance

A DFSDM peripheral instance.

NextChannel

Per-instance “successor” transceiver.

NextChannelForInstance

Links a transceiver marker to the next channel’s marker (modulo the instance channel count).

NonEmpty

Marker trait to enforce that a const generic N is greater than 0.

PinSet

Type-level pin presence of one transceiver. Exactly three states exist; “clock without data” has no representative and is therefore inexpressible.

PinSource

Which transceiver’s serial pins this transceiver’s interface consumes (CFGR1.CHINSEL). Pins are borrowed from that transceiver’s slot, so acquire/release live there too (see Drop).

PowerState

Marker trait for power-state

SerialMode

Marker for modes that carry a serial stream a delay-block pulse skipper can act on. Not implemented for the parallel-input modes (ParallelAdcMode, ParallelStandard, ParallelInterleaved, ParallelPaired).

Shape

Configuration shape: maps a transceiver count to its selector bundle.

TransceiverMarker

TransceiverTrait

Erases all transceivers of an instance into one type, for filter configuration.

TriggerSource

A trigger source that can drive filter M on instance T.