Module npu 

NPU — ST Neural-ART accelerator (“ATON”) of the STM32N6.

The Neural-ART NPU is a data-flow machine: convolution accelerators, activation/pooling/arithmetic units and DMA “streaming engines” connected by a stream switch. For inference, ST’s Edge AI tooling compiles a network into epochs — self-contained hardware schedules. With the (default, recommended) --enable-epoch-controller option, each hardware epoch is emitted as a blob: a command stream that the NPU’s built-in epoch controller unit executes autonomously, programming all units and raising an interrupt when the epoch completes. The CPU’s job is reduced to:

1. load (and optionally relocate/patch) the blobs — see ecloader,
2. point the epoch controller at a blob and start it,
3. sleep until the end-of-epoch interrupt,
4. run any interleaved software epochs (CPU-side operators emitted by the tool, e.g. a final dequantize) and cache maintenance callbacks,
5. repeat for the next epoch block.

This driver implements that execution model, mirroring ST’s LL_ATON runtime (LL_ATON_RT_RunEpochBlock + ATON_STD_IRQHandler) with an async API. Networks compiled to streaming-engine epochs (without the epoch controller) are not supported.

Prerequisites

System-level setup that the driver deliberately leaves to board/startup code, matching the split in ST’s examples:

• NPU RAMs (AXISRAM3..6) powered and clocked, if the network’s memory pools live there (RCC.MEMENR, RAMCFG).
• When running with TrustZone / RIF: the NPU (and NPU cache) bus masters granted access to the memories holding weights and activations.
• Input/output/blob buffers placed in NPU-visible memory, respecting the cache rules below.
• The NPU cache should be enabled (cache::npu_cache_enable) when weights live in cacheable external memory (flash/PSRAM).

Caches

Buffers shared between CPU and NPU need explicit maintenance; the cache submodule provides both MCU-side (Cortex-M55 D-cache) and NPU-side (CACHEAXI) operations. ST Edge AI generates the required calls as per-epoch callbacks — port them into the epoch’s start/end functions.

Example

use embassy_stm32::{bind_interrupts, npu, peripherals};
use embassy_stm32::npu::ecloader::EcBinary;

bind_interrupts!(struct Irqs {
    NPU0 => npu::InterruptHandler<peripherals::NPU>;
});

// EC binary generated by ST Edge AI (`<network>_ecblobs.h`, here included
// as a u64 array) and a writable, NPU-visible copy of its blob.
static EC_BIN: &[u64] = &[/* ... */];
static BLOB: StaticCell<[u64; 3800]> = StaticCell::new();

let p = embassy_stm32::init(Default::default());
let mut npu = npu::Npu::new(p.NPU, Irqs);

// Network init: load the blob, relocate its "user input" symbol to the
// actual input buffer (mirrors LL_ATON_EC_Network/Inference_Init_*).
let bin = EcBinary::new(EC_BIN).unwrap();
let blob = BLOB.init([0; 3800]);
bin.load_blob(blob).unwrap();
let mut prev_base = 0;
bin.reloc_by_id(blob, "_user_io_input_0", input_buf.as_ptr() as u32, &mut prev_base).unwrap();

// Inference: run the epoch list of the network.
npu.run_epoch_blob(blob).await.unwrap();

For multi-epoch networks, Npu::run_network executes a list of EpochBlocks (hardware blobs interleaved with software epochs), which is the direct equivalent of the generated EpochBlock_ItemTypeDef array.

Modules

cache

Cache maintenance for NPU inference.

ecloader

Loader for ST Edge AI Epoch Controller binaries.

regs

Raw ATON register map. Exposed as an intentional low-level route for advanced users that need to compose their own streaming-engine helpers on top of the epoch-controller-oriented driver (e.g. a hardware-DMA transpose). Names mirror the ATON reference-manual naming; no stability guarantees are made about this module. Minimal register map for the ST Neural-ART accelerator (“ATON”) on STM32N6.

Structs

EpochBlock

One entry of a network’s epoch list — the Rust equivalent of the generated EpochBlock_ItemTypeDef.

InterruptHandler

Interrupt handler for ATON interrupt line 0 (NVIC NPU0).

Npu

Neural-ART NPU driver.

Enums

Error

NPU error.

Traits

Instance

NPU instance.