Module regs 

Raw ATON register map. Exposed as an intentional low-level route for advanced users that need to compose their own streaming-engine helpers on top of the epoch-controller-oriented driver (e.g. a hardware-DMA transpose). Names mirror the ATON reference-manual naming; no stability guarantees are made about this module. Minimal register map for the ST Neural-ART accelerator (“ATON”) on STM32N6.

Why this is not stm32_metapac::npu

Embassy’s usual convention is to reach peripherals through crate::pac::* (i.e. stm32-metapac, which is generated from stm32-data chiptool YAML, which in turn is derived from ST’s SVDs plus hand-authored overrides). The STM32N657 SVD ST publishes today (checked against STM32N657.svd) does describe the NPU at the system integration level — the five NVIC lines (NPU_end_of_epoch, NPU1..3, NPUCACHE) and the RCC bits (NPUEN, NPURST, NPUCACHEEN, NPULPEN, …) are all there and reachable via stm32-metapac as usual. What is not described is the ATON register block itself at 0x480E_0000: no <peripheral> entry for the epoch controller, streaming engines, stream switch, bus interfaces, interrupt controller or cache maintenance unit. That is roughly 140 KB of register space that the reference manual documents but the SVD does not.

Names, offsets and bit positions are taken from the generated ATON.h of the STM32N6 (Neural-ART machine description, ATON IP v1.x) as shipped with ST Edge AI / X-CUBE-AI.

Clock/reset gating and NVIC unmasking still go through metapac (RCC and crate::interrupt::typelevel::NPU*) — only the ATON-internal register map is hand-rolled.

Only the units the epoch-controller execution model touches are described:

• CLKCTRL — ATON-internal clock controller (unit clock gates)
• INTCTRL — ATON interrupt controller (4 output lines -> NVIC NPU0..3)
• BUSIF — 2 bus interface units (must be enabled for any traffic)
• STRENG — 10 streaming engines (only the IRQ register, for acks)
• EPOCHCTRL — the epoch controller, which executes command blobs

Register-name docs are omitted: identifiers mirror the ATON reference-manual naming (<UNIT>_<REG>_<FIELD>_<LSB|EN|MASK>), so a per-item doc string would just repeat the name. See the top-of-file summary for the semantics.

Constants

ATON_BASE

ATON register block base address (non-secure alias, matches the address space used by stm32-metapac for the N6 family). NPU_BASE_NS = PERIPH_BASE_NS (0x4000_0000) + 0x0802_0000 + 0x000C_0000.

BUSIF_BASE

BUSIF_CTRL_EN

BUSIF_NUM

Number of bus interface units.

CLKCTRL_AGATES0

Group-A clock gates (always-on infrastructure clocks), bits [31:0].

CLKCTRL_AGATES1

Group-A clock gates, upper word.

CLKCTRL_BASE

CLKCTRL_BGATES

Group-B clock gates (one per accelerator unit; 27 used on N6).

CLKCTRL_CTRL

Clock controller CTRL register. Bit 0 = EN, bit 1 = CLR.

CLKCTRL_CTRL_CLR

CLKCTRL_CTRL_EN

EPOCHCTRL_ADDR

Blob start address (must be 8-byte aligned, points at the blob magic).

EPOCHCTRL_BASE

EPOCHCTRL_BC

Opcode counter (debug).

EPOCHCTRL_CTRL

Epoch controller CTRL. Bit 0 = EN, bit 1 = CLR, bit 3 = SM (step mode), bit 30 = CONFCLR, bit 31 = RUNNING (read-only).

EPOCHCTRL_CTRL_CLR

EPOCHCTRL_CTRL_CONFCLR

EPOCHCTRL_CTRL_EN

EPOCHCTRL_CTRL_RUNNING

EPOCHCTRL_CTRL_SM

EPOCHCTRL_IRQ

Epoch controller IRQ status (write back the read value to ack).

EPOCHCTRL_LABEL

Label register (debug: label of the current/last executed blob section).

INTCTRL_BASE

INTCTRL_CTRL

Interrupt controller CTRL. Bit 0 = EN, bit 1 = CLR, bit 30 = CONFCLR.

INTCTRL_CTRL_CLR

INTCTRL_CTRL_CONFCLR

INTCTRL_CTRL_EN

INTCTRL_INTCLR

Interrupt clear (write 1 to clear latched bits).

INTCTRL_INTREG

Latched interrupt status (one bit per ATON interrupt source).

INTCTRL_INTSET

Software interrupt set.

INT_BUSIF_ERR_MASK

Bus interface error interrupts (BUSIF0 = bit 25, BUSIF1 = bit 26).

INT_BUSIF_ERR_SHIFT

INT_ECTRL_ERR

Epoch controller error (illegal opcode, bus error, …).

INT_ECTRL_EVT

Epoch controller “epoch interrupt” (EPOCH_INT instruction / end of blob).

INT_ECTRL_NOACK

Epoch controller missing-acknowledge error.

INT_STRENG_ERR_MASK

Streaming engine error events, bits 10..=19.

INT_STRENG_ERR_SHIFT

INT_STRENG_EVT_MASK

Streaming engine completion events, bits 0..=9.

STRENG_ADDR_OFF

STRENG_BASE

STRENG_CID_CACHE_OFF

STRENG_CTRL_CLR

STRENG_CTRL_CONFCLR

STRENG_CTRL_CONT

STRENG_CTRL_DIR

STRENG_CTRL_EN

STRENG_CTRL_LSBMODE

STRENG_CTRL_NOBLK

STRENG_CTRL_NOINC

STRENG_CTRL_OFF

STRENG_CTRL_RAW

STRENG_CTRL_RUNNING

STRENG_CTRL_SIGNEXT

STRENG_CTRL_SINGLE

STRENG_CTRL_SIZE0_LSB

STRENG_CTRL_SIZE1_LSB

STRENG_CTRL_SIZE2_LSB

STRENG_DEPTH_OFF

STRENG_DEPTH_OFFSET_LSB

STRENG_DESCRADDR_OFF

STRENG_EVENT_EN_ILLCFG

STRENG_EVENT_EN_OFLOW_ADD

STRENG_EVENT_EN_OFLOW_FRM

STRENG_EVENT_OFF

STRENG_EXTSYNC2_OFF

STRENG_EXTSYNC_OFF

STRENG_FOFFSET_OFF

STRENG_FRAME_RPT_OFF

STRENG_FRPTOFF_OFF

STRENG_FSIZE_HEIGHT_LSB

STRENG_FSIZE_OFF

STRENG_IRQ_OFF

STRENG_LIMITADDR_OFF

STRENG_LIMITEN_ADDRLIMIT

STRENG_LIMITEN_DOFF_MSB_LSB

STRENG_LIMITEN_FRAMELIMIT

STRENG_LIMITEN_OFF

STRENG_LIMITEN_STOPPREFTC

STRENG_LIMIT_OFF

STRENG_NUM

Number of streaming engines.

STRENG_POS_OFF

STRENG_STOPTAG_OFF

STRENG_STRD_OFF

STRSWITCH_BASE

STRSWITCH_CTRL

Stream switch CTRL. Bit 0 = EN, bit 1 = CLR, bit 30 = CONFCLR.

STRSWITCH_CTRL_CLR

STRSWITCH_CTRL_CONFCLR

STRSWITCH_CTRL_EN

STRSW_DST_EN0

STRSW_DST_LINK0_LSB

Functions

busif_ctrl

busif_err

intctrl_intandmsk

AND-mask for interrupt line line (0..=3). The line fires when all sources left enabled (bit = 0) are pending simultaneously; the reset value of all-ones disables the AND group entirely.

intctrl_intormsk

OR-mask for interrupt line line (0..=3). A 1 bit disables the corresponding source on that line; sources left at 0 raise the line whenever pending (“OR” semantics).

modify

read

streng_irq

Streaming engine IRQ status register (write back the read value to ack).

streng_reg

strsw_dst_idx_streng

Destination-index in the stream switch DST-register array for STRENG n (matches ATON_STRSWITCH_0_DSTSTRENG_n_0_IDX == n).

strsw_src_streng

Source-port ID for STRENG n (matches ATON_STRSWITCH_0_LINK_STRENG_n_0 == n).

strswitch_dst

Stream-switch destination-port register for destination index idx (0..=40). Layout is two independent 16-bit sub-contexts: ctx 0: EN0=bit0, LINK0=bits[6:1] (source port id), FNR0=bits[15:8] ctx 1: EN1=bit16, LINK1=bits[22:17], FNR1=bits[31:24]

write