Expand description
Instruction cache (ICACHE)
ICACHE speeds up instruction fetches from external memories (e.g. OCTOSPI/XSPI-mapped
flash) by caching them in a small internal RAM. It has no independent clock gate — it’s
always clocked whenever the CPU is — so unlike most other peripherals, Icache::new()
does not call rcc::enable_and_reset.
Supported on STM32U5, U3, WBA, H5, L5 and N6. On N6 the cache doesn’t support memory
remapping (no CRR registers), so [Icache::enable_remap_region()] and
[Icache::disable_remap_region()] aren’t available there — those methods only exist on
chips whose ICACHE block has region-remap support.
Structs§
- Icache
- Instruction cache driver.
Enums§
- Associativity
- Cache set-associativity.
- Monitor
- Which of the two independent hit/miss performance counters to operate on.