Module tamp 

Tamper detection (TAMP)

The TAMP peripheral monitors external tamper pins and a set of chip-internal tamper conditions, latching a sticky status flag and (optionally) an interrupt when one fires. It also owns a set of backup registers and (on most supported chips) a monotonic counter that live in the backup domain.

TAMP has no independent clock gate: it is always clocked whenever the backup domain is powered, and the backup domain write protection is unlocked unconditionally during crate::init(). So, unlike most other peripherals, Tamp::new() does not call rcc::enable_and_reset.

Supported on STM32G0, G4, H5, L5, U5, WBA and WL. The underlying register layout differs meaningfully across these (channel/tamper counts, whether there’s a monotonic counter, and — on H5 — internal tampers are exposed as individually named bit fields rather than an indexed array); those differences are handled internally and don’t show up in the public API.

Structs

ExternalTamperConfig

Configuration for an external tamper channel.

ExternalTamperPin

A GPIO pin bound to an external tamper channel.

InternalTamper

One of the chip’s internal tamper detection conditions (ITAMPx).

InterruptHandler

Interrupt handler.

Tamp

Tamper detection driver.

TamperStatus

Snapshot of which tamper channels/conditions have a latched detection flag.

Enums

Filter

Tamper input debounce filter, shared by all external tamper channels (FLTCR.TAMPFLT).

Trigger

Active level that triggers a tamper detection event on an external channel.