Struct Misc 

#[repr(transparent)]
pub struct Misc(pub u32);

TSI Miscellaneous Register. DPD_MODE_ENABLE=1 updates the 3 V domain configuration latch; 0 holds it. CAP_BANK_148FF is named in fF but 59.6.1.26 gives pF values; see source conflict note, do not infer a unit conversion from its name.

Tuple Fields

0: u32

Implementations

impl Misc

pub const fn cap_bank_2500ff(&self) -> u8

Enable the 2500fF caps inside cap bank. Encodings: 0: Enable another 2.5 pF in cap bank; 1: Enable another 5.0 pF in cap bank; 2: Enable another 7.5 pF in cap bank; 3: Enable another 10 pF in cap bank; 4: Enable another 12.5 pF in cap bank; 5: Enable another 15 pF in cap bank; 6: Enable another 17.5 pF in cap bank; 7: Enable another 20 pF in cap bank

pub const fn set_cap_bank_2500ff(&mut self, val: u8)

Enable the 2500fF caps inside cap bank. Encodings: 0: Enable another 2.5 pF in cap bank; 1: Enable another 5.0 pF in cap bank; 2: Enable another 7.5 pF in cap bank; 3: Enable another 10 pF in cap bank; 4: Enable another 12.5 pF in cap bank; 5: Enable another 15 pF in cap bank; 6: Enable another 17.5 pF in cap bank; 7: Enable another 20 pF in cap bank

pub const fn cap_bank_312ff(&self) -> u8

Enable the 312fF caps inside cap bank. Encodings: 0: Enable another 0.3125 pF; 1: Enable another 0.625 pF; 2: Enable another 0.936 pF; 3: Enable another 1.25 pF; 4: Enable another 1.56 pF; 5: Enable another 1.87 pF; 6: Enable another 2.19 pF; 7: Enable another 2.5 pF

pub const fn set_cap_bank_312ff(&mut self, val: u8)

Enable the 312fF caps inside cap bank. Encodings: 0: Enable another 0.3125 pF; 1: Enable another 0.625 pF; 2: Enable another 0.936 pF; 3: Enable another 1.25 pF; 4: Enable another 1.56 pF; 5: Enable another 1.87 pF; 6: Enable another 2.19 pF; 7: Enable another 2.5 pF

pub const fn dpd_mode_enable(&self) -> bool

DPD_MODE_ENABLE. Encodings: 0: Configuration information in 3v domain logic is latched; 1: Configuration information in 3v domain logic is updating from configuration registers simultaneously

pub const fn set_dpd_mode_enable(&mut self, val: bool)

DPD_MODE_ENABLE. Encodings: 0: Configuration information in 3v domain logic is latched; 1: Configuration information in 3v domain logic is updating from configuration registers simultaneously

pub const fn cap_bank_148ff(&self) -> u8

CAP_BANK_148FF. Encodings: 0: Enable another 148 pF in cap bank; 1: Enable another 296 pF in cap bank; 2: Enable another 444 pF in cap bank; 3: Enable another 592 pF in cap bank; 4: Enable another 740 pF in cap bank; 5: Enable another 888 pF in cap bank; 6: Enable another 1036 pF in cap bank; 7: Enable another 1184 pF in cap bank

pub const fn set_cap_bank_148ff(&mut self, val: u8)

CAP_BANK_148FF. Encodings: 0: Enable another 148 pF in cap bank; 1: Enable another 296 pF in cap bank; 2: Enable another 444 pF in cap bank; 3: Enable another 592 pF in cap bank; 4: Enable another 740 pF in cap bank; 5: Enable another 888 pF in cap bank; 6: Enable another 1036 pF in cap bank; 7: Enable another 1184 pF in cap bank

pub const fn cap_bank_en(&self) -> bool

Cap bank function enable signal. Encodings: 0: Disable cap bank function; 1: Enable cap bank function

pub const fn set_cap_bank_en(&mut self, val: bool)

Cap bank function enable signal. Encodings: 0: Disable cap bank function; 1: Enable cap bank function

pub const fn clk_divider(&self) -> u8

TSI Clock Divider

pub const fn set_clk_divider(&mut self, val: u8)

TSI Clock Divider

pub const fn counting_clk_high(&self) -> bool

COUNTING_CLK_HIGH. Encodings: 0: Using default process inside SSC; 1: Follow the counting signal from AIP front end

pub const fn set_counting_clk_high(&mut self, val: bool)

COUNTING_CLK_HIGH. Encodings: 0: Using default process inside SSC; 1: Follow the counting signal from AIP front end

Trait Implementations

impl Clone for Misc

fn clone(&self) -> Misc

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Misc

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Misc

fn default() -> Misc

Returns the “default value” for a type.

impl PartialEq for Misc

fn eq(&self, other: &Misc) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Misc

impl Eq for Misc

impl StructuralPartialEq for Misc