Expand description
Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))
Structs§
- Baseline
- TSI Baseline Register. The manual inconsistently labels THRESHOLD_TRACE_EN reserved while listing enable values, and lists both BASE_TRACE_EN encodings reserved despite describing low-power tracing. Fields are raw descriptions, not an assurance of supported tracing. THESHOLD_RATIO references an otherwise undocumented TEST_FINGER_EN.
- Config
- TSI CONFIG Register (TSI_CONFIG) for self-capacitor. Self-capacitor view of offset 0, selected by MODE=0; aliases CONFIG_MUTUAL. Do not set S_SEN and S_NOISE together (59.3.2).
- Config
Mutual - TSI CONFIG register (TSI_CONFIG) for mutual-capacitor (CONFIG_MUTUAL). Mutual-capacitor view of offset 0, selected by MODE=1; aliases CONFIG. The manual reset image is 0x2802007E, including MODE=0: this is a bank reset image, not a ready-to-write mutual-mode configuration. M_PMIRRORR and M_NMIRROR must match.
- Data
- TSI Data and Status Register. TSICNT is read-only. EOSF, OVERRUNF, OUTRGF and DPD_OUTRGF are write-one-to-clear: write only intended flag bits, not read-modify-write. DMA transfer clears EOSF/OUTRGF automatically. DPD_OUTRGF can be read only with GENCS.TSIEN_DPD=1. OVERRUNF encoding descriptions contradict the assertion prose; no polarity enum is supplied.
- Gencs
- TSI General Control and Status Register. TSIEN and STM must not change during a scan. SWTS is a write-only start strobe, reading zero; it starts a software scan when STM=0. Clear DATA.EOSF before ESOR, and DATA.OUTRGF before OUTRG_EN or DMAEN_OUTRG. ACTIVE use requires TSIEN_DPD=0, TSIEN=1 and SPC configuration; low-power scan supports channels 0-3 and wakes through WUU, not the NVIC (59.1.3).
- Misc
- TSI Miscellaneous Register. DPD_MODE_ENABLE=1 updates the 3 V domain configuration latch; 0 holds it. CAP_BANK_148FF is named in fF but 59.6.1.26 gives pF values; see source conflict note, do not infer a unit conversion from its name.
- Mul
- TSI Mutual-cap Register. M_TRIM_USED[31:16] is omitted: 59.6.1.6 calls it “Not use, just reserved”, despite the XML exposing it. M_MODE=3 is not allowed.
- Mutual
RxSel310 - Mutual RX mode channels selection(CH31~CH0)
- Mutual
RxSel6332 - Mutual RX mode channels selection(CH63~CH32)
- Mutual
RxSel6964 - Mutual RX mode channels selection (CH69~CH64)
- Mutual
TxSel310 - Mutual TX mode channels selection(CH31~CH0)
- Mutual
TxSel6332 - Mutual TX mode channels selection(CH63~CH32)
- Mutual
TxSel6964 - Mutual TX mode channels selection(CH69~CH64)
- Self
Sel310 - Self-cap mode channels selection(CH31~CH0)
- Self
Sel6332 - Self-cap mode channels selection(CH63~CH32)
- Self
Sel6964 - Self-cap mode channels selection(CH69~CH64)
- Shield
- TSI Shield Register. M_SEN_RES has only example values 0, 1, 2 and 14; the source does not establish a complete resistor conversion for all 6-bit values. Kept numeric without inventing holes or a formula.
- Shield
Sel310 - Shield mode channels selection(CH31~CH0)
- Shield
Sel6332 - Shield mode channels selection(CH63~CH32)
- Shield
Sel6964 - Shield mode channels selection(CH69~CH64)
- Sinc
- TSI SINC Filter Register. Low four bits report SSC/filter state; configuration is in bits 16 and above. SINC_CUTOFF encodings 8-15 are NC. Its prose says default div=0 while code 0 is listed as div=1; preserve the raw code rather than interpreting the inconsistent default wording.
- Ssc0
- TSI SSC Register 0
- Ssc1
- TSI SSC Register 1
- Ssc2
- TSI SSC Register 2
- Test
- TSI TEST Register. TSI_TEST_EN is asserted only by a full-register write of 0x55AA55AA, not by setting bit 0; writing bit 0 to zero disables test mode. DPD_TEST_EOSF is write-one-to-clear. CLKSOC_SEL and RUN_CTRL require ipt_test_mod=1; the referenced test guide is not supplied and CLKSOC_SEL values are reserved. This register model does not authorize hardware test operations.
- Trig
- TSI AUTO TRIG Register
- Tshd
- TSI Threshold Register
- Tsi
- Touch sensing input, TSI0 at 0x400C3000. Up to 70 channel-selection bits; actual bonded pins depend on device/package. Select at most one role per channel.