#[repr(transparent)]pub struct Ssc2(pub u32);Expand description
TSI SSC Register 2
Tuple Fields§
§0: u32Implementations§
Source§impl Ssc2
impl Ssc2
Sourcepub const fn move_repeat_num(&self) -> u8
pub const fn move_repeat_num(&self) -> u8
Numeric repeat count code; only codes 0..6 (1..7 cycles) are listed in 59.6.1.10. Other codes are unspecified; no partial seven-entry enum.
Sourcepub const fn set_move_repeat_num(&mut self, val: u8)
pub const fn set_move_repeat_num(&mut self, val: u8)
Numeric repeat count code; only codes 0..6 (1..7 cycles) are listed in 59.6.1.10. Other codes are unspecified; no partial seven-entry enum.
Sourcepub const fn move_steps_num(&self) -> u8
pub const fn move_steps_num(&self) -> u8
MOVE_STEPS_NUM. Encodings: 0: The added value for up-down counter is 0; 1: The added value for up-down counter is 1; 2: The added value for up-down counter is 2; 3: The added value for up-down counter is 3; 4: The added value for up-down counter is 4; 5: The added value for up-down counter is 5; 6: The added value for up-down counter is 6; 7: The added value for up-down counter is 7
Sourcepub const fn set_move_steps_num(&mut self, val: u8)
pub const fn set_move_steps_num(&mut self, val: u8)
MOVE_STEPS_NUM. Encodings: 0: The added value for up-down counter is 0; 1: The added value for up-down counter is 1; 2: The added value for up-down counter is 2; 3: The added value for up-down counter is 3; 4: The added value for up-down counter is 4; 5: The added value for up-down counter is 5; 6: The added value for up-down counter is 6; 7: The added value for up-down counter is 7
Sourcepub const fn move_nocharge_max(&self) -> u8
pub const fn move_nocharge_max(&self) -> u8
MOVE_NOCHARGE_MAX
Sourcepub const fn set_move_nocharge_max(&mut self, val: u8)
pub const fn set_move_nocharge_max(&mut self, val: u8)
MOVE_NOCHARGE_MAX
Sourcepub const fn move_nocharge_min(&self) -> u8
pub const fn move_nocharge_min(&self) -> u8
MOVE_NOCHARGE_MIN. Encodings: 0: The SSC output bit 1’s min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of system clock; 1: The SSC output bit 1’s min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 2: The SSC output bit 1’s min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 3: The SSC output bit 1’s min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 4: The SSC output bit 1’s min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 5: The SSC output bit 1’s min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 6: The SSC output bit 1’s min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 7: The SSC output bit 1’s min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 8: The SSC output bit 1’s min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 9: The SSC output bit 1’s min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 10: The SSC output bit 1’s min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 11: The SSC output bit 1’s min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 12: The SSC output bit 1’s min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 13: The SSC output bit 1’s min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 14: The SSC output bit 1’s min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 15: The SSC output bit 1’s min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock
Sourcepub const fn set_move_nocharge_min(&mut self, val: u8)
pub const fn set_move_nocharge_min(&mut self, val: u8)
MOVE_NOCHARGE_MIN. Encodings: 0: The SSC output bit 1’s min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of system clock; 1: The SSC output bit 1’s min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 2: The SSC output bit 1’s min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 3: The SSC output bit 1’s min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 4: The SSC output bit 1’s min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 5: The SSC output bit 1’s min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 6: The SSC output bit 1’s min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 7: The SSC output bit 1’s min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 8: The SSC output bit 1’s min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 9: The SSC output bit 1’s min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 10: The SSC output bit 1’s min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 11: The SSC output bit 1’s min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 12: The SSC output bit 1’s min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 13: The SSC output bit 1’s min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 14: The SSC output bit 1’s min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock; 15: The SSC output bit 1’s min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock