Module usbphy 

Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))

Structs

Anactrl

Analog Control. F70RM 42.7.15 (text line 106070). Preserve reserved values, including bit 25=1. DEV_PULLDOWN unconditionally enables both 15 kohm pulldowns and must be 0 during normal Device-mode communication and USBHSDCD detection. LVI_EN must be 1 for CLN40ULP PHY. PFD_CLK_SEL codes 0 reference clock, 1 pfd/4, 2 pfd/2, 3 pfd.

AnactrlMask

ANACTRL SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Ctrl

General Purpose Control. F70RM 42.7.5 (text line 104092). Mixed control/read-only status and sticky IRQ flags. Clear HOSTDISCONDETECT_IRQ, OTG_ID_CHG_IRQ, DEVPLUGIN_IRQ and WAKEUP_IRQ by writing 1 to CTRL_CLR (SCT clear space), not by a general write. RESUME_IRQ also supports clearing through a general write; RESUMEIRQSTICKY affects its lifetime. SFTRST is released by writing 0, not self-clearing. Do not set CLKGATE together with SFTRST; reset gates clocks automatically. UTMI_SUSPENDM and OTG_ID_VALUE are read-only. Preserve reserved and no-function bits.

CtrlMask

CTRL SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Debug0

Debug 0. F70RM 42.7.7 (text line 104589). Preserve reserved reset values. HSTPULLDOWN and ENHSTPULLDOWN are independent DP/DM masks: field bit 1 controls DP and bit 0 DM. Values 0..3 are valid combinations, not a two-state enum. OTGIDPIOLOCK holds the sampled OTG ID (not a security lock).

Debug0Mask

DEBUG0 SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Ip

IP Block. F70RM 42.7.9 (text line 104821). Preserve reserved reset values. Do not change POWER_CONTROL_SUSPEND_OPTION without a specific recommendation from NXP.

IpMask

IP SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Pfda

PFD A. F70RM 42.7.17 (text line 106514). Source conflict: six-bit PFD0_FRAC and frequency formula specify n=18..35, but the RM legal-range sentence gives 12-bit values 0x26a..0x27b that cannot fit. Expose raw numeric bits without inventing a corrected range enum. PFD0_CLKGATE=1 gates the output; writing the fractional value toggles pfd_update.

PfdaMask

PFDA SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

PllSic

PLL SIC. F70RM 42.7.10 (text line 104936). Preserve reserved reset values; PLL_LOCK is read-only. PLL_DIV_SEL legal codes 0,1,2,4,5,6,7 select 32,30,24,20,19.2,16,12 MHz; 3 is unusable for USB and 7 may have marginal jitter. PLL_PREDIV optionally divides reference by 2. Enable regulator at least 15 us before PLL_POWER. Main and multiphase clock outputs require PLL_POWER first.

PllSicMask

PLL_SIC SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Pwd

Power Down. F70RM 42.7.2 (text line 103642).

PwdMask

PWD SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Rx

RX Control. F70RM 42.7.4 (text line 103981). ENVADJ and DISCONADJ legal codes are 0..3; codes 4..7 are reserved.

RxMask

RX SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Status

Status. F70RM 42.7.6 (text line 104459). Known reset mask 0xfffffffe, known value 0; OK_STATUS_3V reset is unknown. Generated reset_value is a construction default, not a fixed supply status. OTGID_STATUS is shown writable in XML but the RM diagram shows no writable field: access remains RW per the map, and software-write behavior is not inferred.

TrimOverrideEn

Trim. F70RM 42.7.16 (text line 106288). Known reset mask 0x0000007f, known value 0x7f; bits 31:7 (including factory/external trim values and reserved bits) are unknown. Generated reset_value contains only known bits, not factory trim. Upper trim fields are read-only. Override-control encoding tables specify 0 external/nonvolatile settings, 1 TX/PLL_SIC settings. Several upper-field paragraphs reverse this selection or describe self-selection, conflicting with those tables and the TX/PLL_SIC descriptions; no alternative polarity is guessed.

TrimOverrideEnMask

TRIM_OVERRIDE_EN SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Tx

TX Control. F70RM 42.7.3 (text line 103828). Preserve reserved bits, including 28:26=100b. D_CAL and termination trims are raw 0..15 codes, not a sparse three-value enum. Override selection follows the corresponding TRIM_OVERRIDE_EN control.

TxMask

TX SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Usb1ChrgDetStat

Charger Detect Status. F70RM 42.7.14 (text line 105955). Read-only, including its SET/CLR/TOG address aliases.

Usb1ChrgDetect

Charger Detect. F70RM 42.7.13 (text line 105740). DCDSEL selects manual PHY control (0) or USBHSDCD state machines (1). Disable charger detection before normal USB communication. EN_B and CHK_CHRG_B are active-low enables; CHK_CONTACT and DETECT_SEC are active-high. PULLUP_DP must remain 0 for normal USB and BC 1.2.

Usb1ChrgDetectMask

USB1_CHRG_DETECT SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Usb1VbusDetStat

VBUS Detect Status. F70RM 42.7.12 (text line 105578). Read-only, including its SET/CLR/TOG address aliases. SESSEND is the inverse session-valid result; RM prose says both below/above and the encoding table states 0 above, 1 below. That source conflict is retained explicitly; no voltage-named enum is supplied.

Usb1VbusDetect

VBUS Detect. F70RM 42.7.11 (text line 105240). VBUSVALID_PWRUP_CMPS is a three-bit independent enable mask: bit 0 VBUS_VALID, bit 1 session valid, bit 2 VBUS_VALID_3V; all combinations are legal. VBUS_SOURCE_SEL codes 0 comparator, 1 or 2 session-valid, 3 reserved (unlike USBNC.CTRL2). VBUSVALID_THRESH codes 0..7 select 4.0..4.7 V in 0.1 V steps. Override priority is external before local; local ID override prose has contradictory polarity wording, so no additional boolean interpretation is inferred.

Usb1VbusDetectMask

USB1_VBUS_DETECT SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Usbphy

MCXA5 USB HS PHY. One UTMI+ 16-bit instance; functional only in SD/OD, not MD; CORELDO_VDD_LVL must be >=2. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Version

Version. F70RM 42.7.8 (text line 104763).