Struct PllSicMask 

#[repr(transparent)]
pub struct PllSicMask(pub u32);

PLL_SIC SCT command mask. Zero construction default ensures only explicitly selected bits are written. Register-map hardware reset values are not command payload defaults. Source conflict: RM 42.8 (text lines 106616-106618) says SCT aliases always read 0, must be write-only, and cannot exist for read-only primaries; RM 42.7.1 maps writable primary aliases as RW and also lists aliases of read-only status registers. Mapped access is retained; no reliable alias readback is inferred.

Tuple Fields

0: u32

Implementations

impl PllSicMask

pub const fn misc2_control0(&self) -> bool

Miscellaneous Control. Raw encoding: 0b - Power up PLL; 1b - Power down PLL.

pub const fn set_misc2_control0(&mut self, val: bool)

Miscellaneous Control. Raw encoding: 0b - Power up PLL; 1b - Power down PLL.

pub const fn pll_en_usb_clks(&self) -> bool

PLL Multi-Phase Clock Outputs Enable. Raw encoding: 0b - Disable; 1b - Enable.

pub const fn set_pll_en_usb_clks(&mut self, val: bool)

PLL Multi-Phase Clock Outputs Enable. Raw encoding: 0b - Disable; 1b - Enable.

pub const fn pll_power(&self) -> bool

USB PLL Powerup Control. Raw encoding: 0b - Power down; 1b - Allow powerup.

pub const fn set_pll_power(&mut self, val: bool)

USB PLL Powerup Control. Raw encoding: 0b - Power down; 1b - Allow powerup.

pub const fn pll_enable(&self) -> bool

PLL Output Clock Enable. Raw encoding: 0b - Disable; 1b - Enable.

pub const fn set_pll_enable(&mut self, val: bool)

PLL Output Clock Enable. Raw encoding: 0b - Disable; 1b - Enable.

pub const fn pll_bypass(&self) -> bool

Bypass USB PLL. Raw encoding: 0b - 480 MHz output clock; 1b - Input reference clock.

pub const fn set_pll_bypass(&mut self, val: bool)

Bypass USB PLL. Raw encoding: 0b - 480 MHz output clock; 1b - Input reference clock.

pub const fn refbias_pwd_sel(&self) -> bool

Reference Bias Power Control. Raw encoding: 0b - PLL_POWER internal state signal; 1b - REFBIAS_PWD.

pub const fn set_refbias_pwd_sel(&mut self, val: bool)

Reference Bias Power Control. Raw encoding: 0b - PLL_POWER internal state signal; 1b - REFBIAS_PWD.

pub const fn refbias_pwd(&self) -> bool

Power Down Reference Bias. Raw encoding: 0b - Enable; 1b - Disable or power down.

pub const fn set_refbias_pwd(&mut self, val: bool)

Power Down Reference Bias. Raw encoding: 0b - Enable; 1b - Disable or power down.

pub const fn pll_reg_enable(&self) -> bool

Enable PLL Regulator. Raw encoding: 0b - Disable; 1b - Enable.

pub const fn set_pll_reg_enable(&mut self, val: bool)

Enable PLL Regulator. Raw encoding: 0b - Disable; 1b - Enable.

pub const fn pll_div_sel(&self) -> u8

PLL Divider Value Configuration. Raw encoding: 000b - Configure for a 32 MHz input clock (divide by 15); 001b - Configure for a 30 MHz input clock (divide by 16); 010b - Configure for a 24 MHz input clock (divide by 20); 011b - Reserved, not usable for USB operation (divide by 22); 100b - Configure for a 20 MHz input clock (divide by 24); 101b - Configure for a 19.2 MHz input clock (divide by 25); 110b - Configure for a 16 MHz input clock (divide by 30); 111b - Configure for a 12 MHz input clock (divide by 40).

pub const fn set_pll_div_sel(&mut self, val: u8)

PLL Divider Value Configuration. Raw encoding: 000b - Configure for a 32 MHz input clock (divide by 15); 001b - Configure for a 30 MHz input clock (divide by 16); 010b - Configure for a 24 MHz input clock (divide by 20); 011b - Reserved, not usable for USB operation (divide by 22); 100b - Configure for a 20 MHz input clock (divide by 24); 101b - Configure for a 19.2 MHz input clock (divide by 25); 110b - Configure for a 16 MHz input clock (divide by 30); 111b - Configure for a 12 MHz input clock (divide by 40).

pub const fn pll_prediv(&self) -> bool

PLL Pre-Divider. Raw encoding: 0b - Uses the undivided reference clock for PLL loop; 1b - Divides the reference clock by two for PLL loop.

pub const fn set_pll_prediv(&mut self, val: bool)

PLL Pre-Divider. Raw encoding: 0b - Uses the undivided reference clock for PLL loop; 1b - Divides the reference clock by two for PLL loop.

pub const fn pll_lock(&self) -> bool

USB PLL Lock Status Indicator. Read-only status/value; writes do not configure this field. Raw encoding: 0b - Not locked; 1b - Locked.

pub const fn set_pll_lock(&mut self, val: bool)

USB PLL Lock Status Indicator. Read-only status/value; writes do not configure this field. Raw encoding: 0b - Not locked; 1b - Locked.

Trait Implementations

impl Clone for PllSicMask

fn clone(&self) -> PllSicMask

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for PllSicMask

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for PllSicMask

fn default() -> PllSicMask

Returns the “default value” for a type.

impl PartialEq for PllSicMask

fn eq(&self, other: &PllSicMask) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for PllSicMask

impl Eq for PllSicMask

impl StructuralPartialEq for PllSicMask