#[repr(transparent)]pub struct Anactrl(pub u32);Expand description
Analog Control. F70RM 42.7.15 (text line 106070). Preserve reserved values, including bit 25=1. DEV_PULLDOWN unconditionally enables both 15 kohm pulldowns and must be 0 during normal Device-mode communication and USBHSDCD detection. LVI_EN must be 1 for CLN40ULP PHY. PFD_CLK_SEL codes 0 reference clock, 1 pfd/4, 2 pfd/2, 3 pfd.
Tuple Fields§
§0: u32Implementations§
Source§impl Anactrl
impl Anactrl
Sourcepub const fn lvi_en(&self) -> bool
pub const fn lvi_en(&self) -> bool
Internal Low Voltage Detector Enable. Raw encoding: 0b - Disable; 1b - Enable.
Sourcepub const fn set_lvi_en(&mut self, val: bool)
pub const fn set_lvi_en(&mut self, val: bool)
Internal Low Voltage Detector Enable. Raw encoding: 0b - Disable; 1b - Enable.
Sourcepub const fn pfd_clk_sel(&self) -> u8
pub const fn pfd_clk_sel(&self) -> u8
PFD Clock Selection. Raw encoding: 00b - USB1PFDCLK = USB PLL reference clock; 01b - USB1PFDCLK = pfd_clk ÷ 4; 10b - USB1PFDCLK frequency = pfd_clk ÷ 2; 11b - USB1PFDCLK = pfd_clk.
Sourcepub const fn set_pfd_clk_sel(&mut self, val: u8)
pub const fn set_pfd_clk_sel(&mut self, val: u8)
PFD Clock Selection. Raw encoding: 00b - USB1PFDCLK = USB PLL reference clock; 01b - USB1PFDCLK = pfd_clk ÷ 4; 10b - USB1PFDCLK frequency = pfd_clk ÷ 2; 11b - USB1PFDCLK = pfd_clk.
Sourcepub const fn dev_pulldown(&self) -> bool
pub const fn dev_pulldown(&self) -> bool
Device Pulldown Enable. Raw encoding: 0b - Disable; 1b - Enable.
Sourcepub const fn set_dev_pulldown(&mut self, val: bool)
pub const fn set_dev_pulldown(&mut self, val: bool)
Device Pulldown Enable. Raw encoding: 0b - Disable; 1b - Enable.