Struct Tsi 

pub struct Tsi { /* private fields */ }

Touch sensing input, TSI0 at 0x400C3000. Up to 70 channel-selection bits; actual bonded pins depend on device/package. Select at most one role per channel.

Implementations

impl Tsi

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn config(self) -> Reg<Config, RW>

TSI CONFIG Register (TSI_CONFIG) for self-capacitor. Self-capacitor view of offset 0, selected by MODE=0; aliases CONFIG_MUTUAL. Do not set S_SEN and S_NOISE together (59.3.2).

pub const fn config_mutual(self) -> Reg<ConfigMutual, RW>

TSI CONFIG register (TSI_CONFIG) for mutual-capacitor (CONFIG_MUTUAL). Mutual-capacitor view of offset 0, selected by MODE=1; aliases CONFIG. The manual reset image is 0x2802007E, including MODE=0: this is a bank reset image, not a ready-to-write mutual-mode configuration. M_PMIRRORR and M_NMIRROR must match.

pub const fn tshd(self) -> Reg<Tshd, RW>

TSI Threshold Register

pub const fn gencs(self) -> Reg<Gencs, RW>

TSI General Control and Status Register. TSIEN and STM must not change during a scan. SWTS is a write-only start strobe, reading zero; it starts a software scan when STM=0. Clear DATA.EOSF before ESOR, and DATA.OUTRGF before OUTRG_EN or DMAEN_OUTRG. ACTIVE use requires TSIEN_DPD=0, TSIEN=1 and SPC configuration; low-power scan supports channels 0-3 and wakes through WUU, not the NVIC (59.1.3).

pub const fn mul(self) -> Reg<Mul, RW>

TSI Mutual-cap Register. M_TRIM_USED[31:16] is omitted: 59.6.1.6 calls it “Not use, just reserved”, despite the XML exposing it. M_MODE=3 is not allowed.

pub const fn sinc(self) -> Reg<Sinc, RW>

TSI SINC Filter Register. Low four bits report SSC/filter state; configuration is in bits 16 and above. SINC_CUTOFF encodings 8-15 are NC. Its prose says default div=0 while code 0 is listed as div=1; preserve the raw code rather than interpreting the inconsistent default wording.

pub const fn ssc0(self) -> Reg<Ssc0, RW>

TSI SSC Register 0

pub const fn ssc1(self) -> Reg<Ssc1, RW>

TSI SSC Register 1

pub const fn ssc2(self) -> Reg<Ssc2, RW>

TSI SSC Register 2

pub const fn baseline(self) -> Reg<Baseline, RW>

TSI Baseline Register. The manual inconsistently labels THRESHOLD_TRACE_EN reserved while listing enable values, and lists both BASE_TRACE_EN encodings reserved despite describing low-power tracing. Fields are raw descriptions, not an assurance of supported tracing. THESHOLD_RATIO references an otherwise undocumented TEST_FINGER_EN.

pub const fn shield(self) -> Reg<Shield, RW>

TSI Shield Register. M_SEN_RES has only example values 0, 1, 2 and 14; the source does not establish a complete resistor conversion for all 6-bit values. Kept numeric without inventing holes or a formula.

pub const fn self_sel_31_0(self) -> Reg<SelfSel310, RW>

Self-cap mode channels selection(CH31~CH0)

pub const fn self_sel_63_32(self) -> Reg<SelfSel6332, RW>

Self-cap mode channels selection(CH63~CH32)

pub const fn self_sel_69_64(self) -> Reg<SelfSel6964, RW>

Self-cap mode channels selection(CH69~CH64)

pub const fn shield_sel_31_0(self) -> Reg<ShieldSel310, RW>

Shield mode channels selection(CH31~CH0)

pub const fn shield_sel_63_32(self) -> Reg<ShieldSel6332, RW>

Shield mode channels selection(CH63~CH32)

pub const fn shield_sel_69_64(self) -> Reg<ShieldSel6964, RW>

Shield mode channels selection(CH69~CH64)

pub const fn mutual_tx_sel_31_0(self) -> Reg<MutualTxSel310, RW>

Mutual TX mode channels selection(CH31~CH0)

pub const fn mutual_tx_sel_63_32(self) -> Reg<MutualTxSel6332, RW>

Mutual TX mode channels selection(CH63~CH32)

pub const fn mutual_tx_sel_69_64(self) -> Reg<MutualTxSel6964, RW>

Mutual TX mode channels selection(CH69~CH64)

pub const fn mutual_rx_sel_31_0(self) -> Reg<MutualRxSel310, RW>

Mutual RX mode channels selection(CH31~CH0)

pub const fn mutual_rx_sel_63_32(self) -> Reg<MutualRxSel6332, RW>

Mutual RX mode channels selection(CH63~CH32)

pub const fn mutual_rx_sel_69_64(self) -> Reg<MutualRxSel6964, RW>

Mutual RX mode channels selection (CH69~CH64)

pub const fn data(self) -> Reg<Data, RW>

TSI Data and Status Register. TSICNT is read-only. EOSF, OVERRUNF, OUTRGF and DPD_OUTRGF are write-one-to-clear: write only intended flag bits, not read-modify-write. DMA transfer clears EOSF/OUTRGF automatically. DPD_OUTRGF can be read only with GENCS.TSIEN_DPD=1. OVERRUNF encoding descriptions contradict the assertion prose; no polarity enum is supplied.

pub const fn misc(self) -> Reg<Misc, RW>

TSI Miscellaneous Register. DPD_MODE_ENABLE=1 updates the 3 V domain configuration latch; 0 holds it. CAP_BANK_148FF is named in fF but 59.6.1.26 gives pF values; see source conflict note, do not infer a unit conversion from its name.

pub const fn trig(self) -> Reg<Trig, RW>

TSI AUTO TRIG Register

pub const fn test(self) -> Reg<Test, RW>

TSI TEST Register. TSI_TEST_EN is asserted only by a full-register write of 0x55AA55AA, not by setting bit 0; writing bit 0 to zero disables test mode. DPD_TEST_EOSF is write-one-to-clear. CLKSOC_SEL and RUN_CTRL require ipt_test_mod=1; the referenced test guide is not supplied and CLKSOC_SEL values are reserved. This register model does not authorize hardware test operations.

Trait Implementations

impl Clone for Tsi

fn clone(&self) -> Tsi

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Tsi

fn eq(&self, other: &Tsi) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Tsi

impl Eq for Tsi

impl Send for Tsi

impl StructuralPartialEq for Tsi

impl Sync for Tsi