#[repr(transparent)]pub struct DmaCh0RxInterruptWatchdogTimer(pub u32);Expand description
F70RM Rev. 1 section 51.7.5.12; manual text line 156689.
Tuple Fields§
§0: u32Implementations§
Source§impl DmaCh0RxInterruptWatchdogTimer
impl DmaCh0RxInterruptWatchdogTimer
Sourcepub const fn rwt(&self) -> u8
pub const fn rwt(&self) -> u8
Receive Interrupt Watchdog Timer Count. This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the DMA_CH0_Status register, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet. NOTE This field is not testable by an automated register test.
Sourcepub const fn set_rwt(&mut self, val: u8)
pub const fn set_rwt(&mut self, val: u8)
Receive Interrupt Watchdog Timer Count. This field indicates the number of system clock cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx DMA completes the transfer of a packet for which the RI bit is not set in the DMA_CH0_Status register, because of the setting of Interrupt Enable bit in the corresponding descriptor RDES3[30]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per the Interrupt Enable bit RDES3[30] of any received packet. NOTE This field is not testable by an automated register test.
Sourcepub const fn itw(&self) -> u8
pub const fn itw(&self) -> u8
Rx Idle Timer Window. This field when programmed with a non-zero value, enables operation of the Rx Idle Timer. The timer window is determined in number of system clock cycles when this field is multiplied by the ITCU unit.
Sourcepub const fn set_itw(&mut self, val: u8)
pub const fn set_itw(&mut self, val: u8)
Rx Idle Timer Window. This field when programmed with a non-zero value, enables operation of the Rx Idle Timer. The timer window is determined in number of system clock cycles when this field is multiplied by the ITCU unit.
Sourcepub const fn rwtu(&self) -> u8
pub const fn rwtu(&self) -> u8
Receive Interrupt Watchdog Timer Count Units. This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2’b00: 256 - 2’b01: 512 - 2’b10: 1024 - 2’b11: 2048 For example, when RWT=2 and RWTU=1, the watchdog timer is set for 2*512=1024 system clock cycles. NOTE This field is not testable by an automated register test.
Sourcepub const fn set_rwtu(&mut self, val: u8)
pub const fn set_rwtu(&mut self, val: u8)
Receive Interrupt Watchdog Timer Count Units. This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2’b00: 256 - 2’b01: 512 - 2’b10: 1024 - 2’b11: 2048 For example, when RWT=2 and RWTU=1, the watchdog timer is set for 2*512=1024 system clock cycles. NOTE This field is not testable by an automated register test.
Sourcepub const fn itcu(&self) -> u8
pub const fn itcu(&self) -> u8
Rx Idle Timer Count Units. This fields indicates the number of system clock cycles corresponding to one unit in ITW field. - 2’b00: 256 - 2’b01: 512 - 2’b10: 1024 - 2’b11: 2048 For example, when ITW=01010 and ITCU=1, Rx Idle timer is set for 10*512=5120 system clock cycles. Vendor arithmetic error: the example at manual lines 156761-156762 prints 1024 cycles; 5120 cycles follows the ITW multiplication rule at lines 156790-156792.
Sourcepub const fn set_itcu(&mut self, val: u8)
pub const fn set_itcu(&mut self, val: u8)
Rx Idle Timer Count Units. This fields indicates the number of system clock cycles corresponding to one unit in ITW field. - 2’b00: 256 - 2’b01: 512 - 2’b10: 1024 - 2’b11: 2048 For example, when ITW=01010 and ITCU=1, Rx Idle timer is set for 10*512=5120 system clock cycles. Vendor arithmetic error: the example at manual lines 156761-156762 prints 1024 cycles; 5120 cycles follows the ITW multiplication rule at lines 156790-156792.
Sourcepub const fn rbct(&self) -> u16
pub const fn rbct(&self) -> u16
Receive Byte Count Threshold.. This field sets the limit in number of bytes or number of RX packets (based on PSEL) transferred without the assertion of Receive Interrupt. Once this limit is crossed, Receive interrupt is asserted, and the watchdog timer (corresponding to RWT) is also reset. This function is valid only when set to a non-zero value. When RBCT = 0, RX Packet/Byte counter is inactive. When PSEL = 0, this field is multiplied by 1024, to get the actual number of byte threshold. When PSEL =1, RBCT value is directly used. Thus the maximum limit is 511 packets or 511 x 1024 bytes respectively.
Sourcepub const fn set_rbct(&mut self, val: u16)
pub const fn set_rbct(&mut self, val: u16)
Receive Byte Count Threshold.. This field sets the limit in number of bytes or number of RX packets (based on PSEL) transferred without the assertion of Receive Interrupt. Once this limit is crossed, Receive interrupt is asserted, and the watchdog timer (corresponding to RWT) is also reset. This function is valid only when set to a non-zero value. When RBCT = 0, RX Packet/Byte counter is inactive. When PSEL = 0, this field is multiplied by 1024, to get the actual number of byte threshold. When PSEL =1, RBCT value is directly used. Thus the maximum limit is 511 packets or 511 x 1024 bytes respectively.
Sourcepub const fn psel(&self) -> bool
pub const fn psel(&self) -> bool
Packet Count Interrupt Select.. When this bit is set, RBCT indicates the number of packet threshold at which the Receive Interrupt (RI) is activated and the watchdog timer reset. When this bit is low, RBCT indicates the number of data byte threshold at which the Receive Interrupt (RI) is activated and the watchdog timer reset. - 1: RBCT field is used to generate interrupt based on number of packets received. - 0: RBCT field is used to generate interrupt based on number of bytes received.
Sourcepub const fn set_psel(&mut self, val: bool)
pub const fn set_psel(&mut self, val: bool)
Packet Count Interrupt Select.. When this bit is set, RBCT indicates the number of packet threshold at which the Receive Interrupt (RI) is activated and the watchdog timer reset. When this bit is low, RBCT indicates the number of data byte threshold at which the Receive Interrupt (RI) is activated and the watchdog timer reset. - 1: RBCT field is used to generate interrupt based on number of packets received. - 0: RBCT field is used to generate interrupt based on number of bytes received.
Trait Implementations§
Source§impl Clone for DmaCh0RxInterruptWatchdogTimer
impl Clone for DmaCh0RxInterruptWatchdogTimer
Source§fn clone(&self) -> DmaCh0RxInterruptWatchdogTimer
fn clone(&self) -> DmaCh0RxInterruptWatchdogTimer
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moreSource§impl Default for DmaCh0RxInterruptWatchdogTimer
impl Default for DmaCh0RxInterruptWatchdogTimer
Source§fn default() -> DmaCh0RxInterruptWatchdogTimer
fn default() -> DmaCh0RxInterruptWatchdogTimer
Source§impl PartialEq for DmaCh0RxInterruptWatchdogTimer
impl PartialEq for DmaCh0RxInterruptWatchdogTimer
Source§fn eq(&self, other: &DmaCh0RxInterruptWatchdogTimer) -> bool
fn eq(&self, other: &DmaCh0RxInterruptWatchdogTimer) -> bool
self and other values to be equal, and is used by ==.