Struct DmaCh0TxControl 

#[repr(transparent)]
pub struct DmaCh0TxControl(pub u32);

F70RM Rev. 1 section 51.7.5.3; manual text line 155809.

Tuple Fields

0: u32

Implementations

impl DmaCh0TxControl

pub const fn st(&self) -> bool

Start or Stop Transmission Command. - 1: Transmission is placed in the running state. The DMA checks the Tx list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the following positions: - The current position in the list This is the base address of the Transmit list set by the DMA_CH0_TxDesc_List_Address register. - The position at which the transmission was previously stopped If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the DMA_CH0_Status register is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the DMA_CH0_TxDesc_List_Address register, the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program DMA_CH0_TxDesc_List_Address register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. NOTE This field is not testable by an automated register test. 0b - Stop Transmission Command 1b - Start Transmission Command

pub const fn set_st(&mut self, val: bool)

Start or Stop Transmission Command. - 1: Transmission is placed in the running state. The DMA checks the Tx list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the following positions: - The current position in the list This is the base address of the Transmit list set by the DMA_CH0_TxDesc_List_Address register. - The position at which the transmission was previously stopped If the DMA does not own the current descriptor, the transmission enters the Suspended state and the TBU bit of the DMA_CH0_Status register is set. The Start Transmission command is effective only when the transmission is stopped. If the command is issued before setting the DMA_CH0_TxDesc_List_Address register, the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current packet. The Next Descriptor position in the Transmit list is saved, and it becomes the current position when the transmission is restarted. To change the list address, you need to program DMA_CH0_TxDesc_List_Address register with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current packet is complete or the transmission is in the Suspended state. NOTE This field is not testable by an automated register test. 0b - Stop Transmission Command 1b - Start Transmission Command

pub const fn osf(&self) -> bool

Operate on Second Packet. - 1: Instructs the DMA to process the second packet of the Tx data even before the status for the first packet is obtained. 0b - Operate on Second Packet disabled 1b - Operate on Second Packet enabled

pub const fn set_osf(&mut self, val: bool)

Operate on Second Packet. - 1: Instructs the DMA to process the second packet of the Tx data even before the status for the first packet is obtained. 0b - Operate on Second Packet disabled 1b - Operate on Second Packet enabled

pub const fn txpbl(&self) -> u8

Transmit Programmable Burst Length. These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: 1. Set the 8xPBL mode in DMA_CH0_Control register. 2. Set the TxPBL. Note: The maximum value of TxPBL must be less than or equal to half the Tx Queue size (TQS field of MTL_TxQ0_Operation_Mode register) in terms of beats. This is required so that the Tx Queue has space to store at least another Tx PBL worth of data while the MTL Tx Queue Controller is transferring data to MAC. For example, in 32-bit data width configurations the total locations in Tx Queue of size 512 bytes is 128, TxPBL and 8xPBL needs to be programmed to less than or equal to 64.

pub const fn set_txpbl(&mut self, val: u8)

Transmit Programmable Burst Length. These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus. You can program PBL with any of the following values: 1, 2, 4, 8, 16, or 32. Any other value results in undefined behavior. To transfer more than 32 beats, perform the following steps: 1. Set the 8xPBL mode in DMA_CH0_Control register. 2. Set the TxPBL. Note: The maximum value of TxPBL must be less than or equal to half the Tx Queue size (TQS field of MTL_TxQ0_Operation_Mode register) in terms of beats. This is required so that the Tx Queue has space to store at least another Tx PBL worth of data while the MTL Tx Queue Controller is transferring data to MAC. For example, in 32-bit data width configurations the total locations in Tx Queue of size 512 bytes is 128, TxPBL and 8xPBL needs to be programmed to less than or equal to 64.

pub const fn etic(&self) -> bool

Early Transmit Interrupt Control. - 1: Early Transmit Interrupt (ETI) status = 1 after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) = 1. - 0: Early Transmit Interrupt (ETI) status = 1 only after a complete packet is transferred to the MTL Tx FIFO memory. 0b - Early Transmit Interrupt is disabled 1b - Early Transmit Interrupt is enabled

pub const fn set_etic(&mut self, val: bool)

Early Transmit Interrupt Control. - 1: Early Transmit Interrupt (ETI) status = 1 after completion of transfer of data from buffers of a transmit descriptor in which IOC bit (TDES2[31]) = 1. - 0: Early Transmit Interrupt (ETI) status = 1 only after a complete packet is transferred to the MTL Tx FIFO memory. 0b - Early Transmit Interrupt is disabled 1b - Early Transmit Interrupt is enabled

Trait Implementations

impl Clone for DmaCh0TxControl

fn clone(&self) -> DmaCh0TxControl

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DmaCh0TxControl

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for DmaCh0TxControl

fn default() -> DmaCh0TxControl

Returns the “default value” for a type.

impl PartialEq for DmaCh0TxControl

fn eq(&self, other: &DmaCh0TxControl) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for DmaCh0TxControl

impl Eq for DmaCh0TxControl

impl StructuralPartialEq for DmaCh0TxControl