Struct MtlTxq0OperationMode

Source

#[repr(transparent)]
pub struct MtlTxq0OperationMode(pub u32);

Expand description

F70RM Rev. 1 section 51.7.3.2; manual text line 154195.

Tuple Fields§

§0: u32

Implementations§

Source §

impl MtlTxq0OperationMode

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pub const fn ftq(&self) -> bool

Timestamp Sub Seconds. Flush Transmit QueueWhen this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you must not write to the MTL_TxQ0_Operation_Mode register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (clk_tx_i) must be active. Access restrictions apply. - MAC initiates the Tx queue flush when application writes 1. - MAC writes 0 after the Tx queue flush is complete. - MAC ignores when application writes 0. NOTE You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the software cannot clear this bit. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0b - Flush Transmit Queue is disabled 1b - Flush Transmit Queue is enabled

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pub const fn set_ftq(&mut self, val: bool)

Timestamp Sub Seconds. Flush Transmit QueueWhen this bit is set, the Tx queue controller logic is reset to its default values. Therefore, all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit is reset, you must not write to the MTL_TxQ0_Operation_Mode register. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt packet transmission. Note: The flush operation is complete only when the Tx queue is empty and the application has accepted the pending Tx Status of all transmitted packets. To complete this flush operation, the PHY Tx clock (clk_tx_i) must be active. Access restrictions apply. - MAC initiates the Tx queue flush when application writes 1. - MAC writes 0 after the Tx queue flush is complete. - MAC ignores when application writes 0. NOTE You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the software cannot clear this bit. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0b - Flush Transmit Queue is disabled 1b - Flush Transmit Queue is enabled

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pub const fn tsf(&self) -> bool

Transmit Store and Forward. When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit must be changed only when the transmission is stopped. 0b - Transmit Store and Forward is disabled 1b - Transmit Store and Forward is enabled

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pub const fn set_tsf(&mut self, val: bool)

Transmit Store and Forward. When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set, the TTC values specified in Bits[6:4] of this register are ignored. This bit must be changed only when the transmission is stopped. 0b - Transmit Store and Forward is disabled 1b - Transmit Store and Forward is enabled

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pub const fn ttc(&self) -> u8

Transmit Threshold Control. These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. 000b - 32 001b - 64 010b - 96 011b - 128 100b - 192 101b - 256 110b - 384 111b - 512

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pub const fn set_ttc(&mut self, val: u8)

Transmit Threshold Control. These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition, full packets with length less than the threshold are also transmitted. These bits are used only when the TSF bit is reset. 000b - 32 001b - 64 010b - 96 011b - 128 100b - 192 101b - 256 110b - 384 111b - 512