Struct Intenset 

#[repr(transparent)]
pub struct Intenset(pub u32);

Interrupt Enable Set. Write-one-to-set interrupt enable bits; port masks are independent bit masks, not one-bit enumerations. Port-local interrupt rules must also be enabled.

Tuple Fields

0: u32

Implementations

impl Intenset

pub const fn portint(&self) -> u8

Port interrupt. Encodings: 1: Corresponding port interrupts main processor, if it matches IRule

pub const fn set_portint(&mut self, val: u8)

Port interrupt. Encodings: 1: Corresponding port interrupts main processor, if it matches IRule

pub const fn p80int(&self) -> bool

Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupts main processor on update from host

pub const fn set_p80int(&mut self, val: bool)

Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupts main processor on update from host

pub const fn busrst(&self) -> bool

Bus Reset. Encodings: 0: Disabled; 1: A change in bus reset status interrupts CPU

pub const fn set_busrst(&mut self, val: bool)

Bus Reset. Encodings: 0: Disabled; 1: A change in bus reset status interrupts CPU

pub const fn irqupd(&self) -> bool

IRQ Update. Encodings: 0: Disabled; 1: Completion of an IRQ update interrupts CPU

pub const fn set_irqupd(&mut self, val: bool)

IRQ Update. Encodings: 0: Disabled; 1: Completion of an IRQ update interrupts CPU

pub const fn wirechg(&self) -> bool

Wire Change. Encodings: 0: Disabled; 1: When one or more VWire inputs have changed, interrupts CPU

pub const fn set_wirechg(&mut self, val: bool)

Wire Change. Encodings: 0: Disabled; 1: When one or more VWire inputs have changed, interrupts CPU

pub const fn hstall(&self) -> bool

Host Stall. Encodings: 0: Disabled; 1: When the MSTAT[HSTALL] is 1, interrupt main processor

pub const fn set_hstall(&mut self, val: bool)

Host Stall. Encodings: 0: Disabled; 1: When the MSTAT[HSTALL] is 1, interrupt main processor

pub const fn crcerr(&self) -> bool

CRC Error. Encodings: 0: Disabled; 1: When CRC error detected, interrupts CPU

pub const fn set_crcerr(&mut self, val: bool)

CRC Error. Encodings: 0: Disabled; 1: When CRC error detected, interrupts CPU

pub const fn gpio(&self) -> bool

GPIO. Encodings: 0: Disabled; 1: When ESPICFG GPIO changes input value, interrupts CPU

pub const fn set_gpio(&mut self, val: bool)

GPIO. Encodings: 0: Disabled; 1: When ESPICFG GPIO changes input value, interrupts CPU

pub const fn cs_int(&self) -> bool

CS_INT. Encodings: 0: Disabled; 1: When CS falls, interrupts the main processor (wake_async is asserted)

pub const fn set_cs_int(&mut self, val: bool)

CS_INT. Encodings: 0: Disabled; 1: When CS falls, interrupts the main processor (wake_async is asserted)

pub const fn cportint(&self) -> u8

Coprocessor Interrupt. Encodings: 0: Disabled; 1: no description available

pub const fn set_cportint(&mut self, val: u8)

Coprocessor Interrupt. Encodings: 0: Disabled; 1: no description available

pub const fn cp80int(&self) -> bool

Coprocessor Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupts coprocessor on update from host

pub const fn set_cp80int(&mut self, val: bool)

Coprocessor Port80 Interrupt. Encodings: 0: Disabled; 1: Port80 interrupts coprocessor on update from host

pub const fn cbusrst(&self) -> bool

Coprocessor Burst. Encodings: 0: Disabled; 1: Change in bus reset status interrupts coprocessor

pub const fn set_cbusrst(&mut self, val: bool)

Coprocessor Burst. Encodings: 0: Disabled; 1: Change in bus reset status interrupts coprocessor

pub const fn cirqupd(&self) -> bool

Coprocessor Interrupt Update. Encodings: 0: Disabled; 1: Completion of an IRQ update interrupts coprocessor

pub const fn set_cirqupd(&mut self, val: bool)

Coprocessor Interrupt Update. Encodings: 0: Disabled; 1: Completion of an IRQ update interrupts coprocessor

pub const fn cwirechg(&self) -> bool

Coprocessor Wire Change. Encodings: 0: Disabled; 1: When one one or more Vwire inputs have changed, interrupts coprocessor

pub const fn set_cwirechg(&mut self, val: bool)

Coprocessor Wire Change. Encodings: 0: Disabled; 1: When one one or more Vwire inputs have changed, interrupts coprocessor

pub const fn chstall(&self) -> bool

Coprocessor Host Stall. Encodings: 0: Disabled; 1: When MSTAT[HSTALL] is 1, interrupts coprocessor

pub const fn set_chstall(&mut self, val: bool)

Coprocessor Host Stall. Encodings: 0: Disabled; 1: When MSTAT[HSTALL] is 1, interrupts coprocessor

pub const fn ccrcerr(&self) -> bool

Coprocessor Error. Encodings: 0: Disabled; 1: When CRC error detected, interrupts coprocessor

pub const fn set_ccrcerr(&mut self, val: bool)

Coprocessor Error. Encodings: 0: Disabled; 1: When CRC error detected, interrupts coprocessor

pub const fn cgpio(&self) -> bool

Coprocessor GPIO. Encodings: 0: Disabled; 1: When ESPICFG GPIO changes input value, interrupts coprocessor

pub const fn set_cgpio(&mut self, val: bool)

Coprocessor GPIO. Encodings: 0: Disabled; 1: When ESPICFG GPIO changes input value, interrupts coprocessor

Trait Implementations

impl Clone for Intenset

fn clone(&self) -> Intenset

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Intenset

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Intenset

fn default() -> Intenset

Returns the “default value” for a type.

impl PartialEq for Intenset

fn eq(&self, other: &Intenset) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Intenset

impl Eq for Intenset

impl StructuralPartialEq for Intenset