Expand description
Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))
Structs§
- Dmactrl
- DMA Control. Two external DMA request channels, with ports 0-4 or Port80. Software primes the first block; DMA enable refills. The function says “up to 3 ports” but 52.3.1.9 and the register expose two DMA requests. The DMA1EN/DMA0EN tables mention action 3 for mailbox while their encoding lists reserve 3; no variant 3 is provided.
- Espi
- eSPI0 target peripheral at 0x4001F000, with five ports and two external DMA request channels. Mode-dependent register aliases are intentional; choose the view matching PCFG.TYPE.
- Espicap
- eSPI Capabilities. Advertised capabilities and limits; host still chooses configuration. SAFERA defines only encodings 0-3 in a four-bit field; other values are unspecified, not inferred. MAXSPD=5-7 is unspecified.
- Espicfg
- eSPI Configuration
- Espimisc
- eSPI Miscellaneous. GPIO_IN is input status; GPIO output controls depend on whether Alert is dedicated. PWRSAV only affects eSPI clock gating, not LPC; may delay writes by less than 200 ns.
- Intenclr
- Interrupt Clear. Alias for clearing the interrupt enables: write one to disable only the intended enables. It does not clear pending event causes.
- Intenset
- Interrupt Enable Set. Write-one-to-set interrupt enable bits; port masks are independent bit masks, not one-bit enumerations. Port-local interrupt rules must also be enabled.
- Intstat
- Masked Interrupt Status. Masked interrupt status is MSTAT AND interrupt enables. The memory map and XML mark RW although the function describes a computed status; no undocumented clear-on-write or read side effect is assumed.
- Irqpush
- IRQ Push. Push an IRQ only after clearing the previous MSTAT.IRQUPD (must be zero). DONE reports completion.
- Mapbase
- Mapped Base
- Mctrl
- Master Control. ENABLE may transition only 0->1/2 or 1/2->0; never directly between active modes or to 3. PENA is a five-port independent enable mask, valid only after port TYPE/configuration is set.
- Mstat
- Master Status. Mixed read-only status and write-one-to-clear sticky causes. PORTINT causes must be handled in PnSTAT. Read, handle data, then clear intended causes; wait at least 50 PCLK cycles before clearing to avoid reassertion (52.8.1.3). Avoid read-modify-write.
- P80stat
- Port 80 Status
- Paddr
- Port Address. Normal-port address view; aliases POMFLEN at each port offset +0x0C. Address alignment must match the port range; split mailbox alignment includes both halves. Do not change address while enabled.
- Pcfg
- Port Configuration. Configure type/address before enabling the port; TYPE must not change while enabled. Only one port may be OOB; if multiple ports are marked OOB, only the lowest-numbered port receives host writes. Only one port may be used for mastering and only one for flash; attempts to configure a second port are refused. Mastering, OOB and flash are not available with LPC. DIRECTION may change with caution. ERRORIGN polarity conflicts between its field and DIRECTION prose. STALLRD/STALLWR are documented here, but 52.4.2 says application stalling is no longer supported: raw fields do not guarantee this feature. TYPE=8 follows the register definition; 52.3.1.3.3 incorrectly calls Mailbox Shared 1010b.
- Pdatain
- Port Data Input. Host input byte for endpoint/index-and-data; otherwise zero-relative last message length, including the four address bytes for SAF. SOURCE CONFLICT: SAF examples (52.6.1 and 52.6.3) require incoming TAG[29:26] and length[11:0], but the register table (52.8.1.27) marks 31:26 reserved and defines DIR[8] with DATA_LEN[7:0]. This model retains the conservative table layout and has no incoming TAG accessor; it does not supply the incoming SAF tag/length view required by those examples. CPU_TAG in PIRULESTAT is an outgoing completion tag, not a replacement for the missing incoming tag. Status depends on data consumption and port type; the source does not completely specify per-read clearing semantics. Mailbox state is explicitly maintained through PIRULESTAT. Do not assume a universal clear-on-read rule.
- Pdataout
- Port Data Out. Output-byte view; aliases PRAMUSE at +0x14. Writing endpoint data makes it pending for the host. The function paragraph repeats input-register wording, but the field definition says data to send to host; the latter is used.
- Pirulestat
- Set Interrupt Rules and User Status. Contains interrupt masks, user status, status commands and completion tags. SRST and SSTCL must not be written together; SRST takes precedence. SSTCL is mode-dependent command bits, not a global enable enum. Program CPU_TAG before completion commands.
- Pomflen
- Port OOB, Mastering, and Flash Length. OOB/master/flash length view; aliases PADDR at +0x0C. LEN is zero-relative; obey host payload limit and maximum 124 bytes, or 120 for bus mastering. Flash erase uses its low three bits as sector encoding. TRANS semantics depend on port type; prepare before issuing SSTCL.
- Pramuse
- Port RAM Use. Mailbox/master RAM-allocation view; aliases PDATAOUT at +0x14. Per-direction length is 4<<LEN bytes (4..512); split mailboxes use twice that RAM. OFF must be aligned modulo the mailbox range.
- Pstat
- Port Status. RDSTAT/WRSTAT depend on port type; change them through PIRULESTAT, not ordinary writes. Interrupt cause bits 8-14 are sticky write-one-to-clear, even with interrupts masked. Clearing INTERR also clears ERR0-ERR3. RPMC_FLASH_DEVICE may toggle for non-RPMC commands and must then be ignored.
- Rambase
- RAM Base. RAM base, at least 4 KiB aligned. Bits 11:0 are always zero and omitted. Map reset is 0x20000000; the function says the system selects the initial base. A generated default is not an observation of allocated memory.
- Rpmc
Support1 - RPMC Support 1. Configure before eSPI starts; do not change while eSPI works. TARGET_RPMC_SUPPORTED is a numeric count: prose says 1-based total up to 63, but the encoding list labels 3 as “up to 63”; no four-entry enum is used.
- Rpmc
Support2 - RPMC Support 2. Configure before eSPI starts; do not change while eSPI works.
- Stataddr
- Status Block Address. Eight-byte status block, aligned to eight bytes. BASE=1/2 is called Base1/Base2 here, whereas MAPBASE and PnADDR use BASE0/BASE1; retain raw numeric BASE because naming conflicts.
- Wirein
Gpio - WIREIN_GPIO. LEVEL and VALID are four independent corresponding bits, not two-state 4-bit values. Captures controller virtual-wire writes; target software forwards them to GPIO.
- Wireout
Gpio - WIREOUT_GPIO. SOURCE CONFLICT: memory map/XML mark read-only, but 52.8.1.21 says the target CPU writes this register to transmit virtual wires. Conservatively retain Read access pending vendor clarification; no write accessor is proposed. LEVEL and VALID are independent bit masks.
- Wirero
- Virtual Wire Host-to-MCU
- Wirewo
- Virtual Wire MCU-to-host. Wait for DONE=1 before writing new wire values. A write clears DONE, hardware sets it after transmission; DONE does not generate an interrupt and must be polled. BOOT_DONE and BOOT_ERRN should be set after power-on. LPC START/FORCE prose does not match all field names; no additional alias fields are invented.