#[repr(transparent)]pub struct Mstat(pub u32);Expand description
Master Status. Mixed read-only status and write-one-to-clear sticky causes. PORTINT causes must be handled in PnSTAT. Read, handle data, then clear intended causes; wait at least 50 PCLK cycles before clearing to avoid reassertion (52.8.1.3). Avoid read-modify-write.
Tuple Fields§
§0: u32Implementations§
Source§impl Mstat
impl Mstat
Sourcepub const fn set_portint(&mut self, val: u8)
pub const fn set_portint(&mut self, val: u8)
Port Interrupt
Sourcepub const fn set_p80int(&mut self, val: bool)
pub const fn set_p80int(&mut self, val: bool)
Port80 Interrupt Request
Sourcepub const fn busrst(&self) -> bool
pub const fn busrst(&self) -> bool
Bus Reset. Encodings: 1: The bit entered or exited reset. Sticky, must clear.
Sourcepub const fn set_busrst(&mut self, val: bool)
pub const fn set_busrst(&mut self, val: bool)
Bus Reset. Encodings: 1: The bit entered or exited reset. Sticky, must clear.
Sourcepub const fn irqupd(&self) -> bool
pub const fn irqupd(&self) -> bool
Interrupt Request Update Completion. Encodings: 1: The bus had an IRQ update completion (for eSPI, IRQPush done; for LPC, SERIRQ done). Sticky, must clear.
Sourcepub const fn set_irqupd(&mut self, val: bool)
pub const fn set_irqupd(&mut self, val: bool)
Interrupt Request Update Completion. Encodings: 1: The bus had an IRQ update completion (for eSPI, IRQPush done; for LPC, SERIRQ done). Sticky, must clear.
Sourcepub const fn wirechg(&self) -> bool
pub const fn wirechg(&self) -> bool
Wire Change. Encodings: 1: For eSPI, one or more input VWires have changed since last cleared for eSPI. For LPC, SERIRQ started. Sticky, write to clear.
Sourcepub const fn set_wirechg(&mut self, val: bool)
pub const fn set_wirechg(&mut self, val: bool)
Wire Change. Encodings: 1: For eSPI, one or more input VWires have changed since last cleared for eSPI. For LPC, SERIRQ started. Sticky, write to clear.
Sourcepub const fn hstall(&self) -> bool
pub const fn hstall(&self) -> bool
Host Stall. Encodings: 1: Host is stalled on a read from or write to a port that has the STALLRD or STALLWR bit set in the PnCFG register. The application must write 1 to this bit to clear and release the host. The stall should not allowed to persist.
Sourcepub const fn set_hstall(&mut self, val: bool)
pub const fn set_hstall(&mut self, val: bool)
Host Stall. Encodings: 1: Host is stalled on a read from or write to a port that has the STALLRD or STALLWR bit set in the PnCFG register. The application must write 1 to this bit to clear and release the host. The stall should not allowed to persist.
Sourcepub const fn crcerr(&self) -> bool
pub const fn crcerr(&self) -> bool
Cyclic Redundancy Check (CRC) Error. Encodings: 1: CRC from the master did not match the computed CRC. The state of the app may be in error (due to bad data). Write 1 to clear.
Sourcepub const fn set_crcerr(&mut self, val: bool)
pub const fn set_crcerr(&mut self, val: bool)
Cyclic Redundancy Check (CRC) Error. Encodings: 1: CRC from the master did not match the computed CRC. The state of the app may be in error (due to bad data). Write 1 to clear.
Sourcepub const fn gpio(&self) -> bool
pub const fn gpio(&self) -> bool
General Purpose Input/Output (GPIO). Encodings: 1: ESPIMISC[GPIO] has had an input change. Only detected if INTENSET has configured this bit to interrupt. Write 1 to clear.
Sourcepub const fn set_gpio(&mut self, val: bool)
pub const fn set_gpio(&mut self, val: bool)
General Purpose Input/Output (GPIO). Encodings: 1: ESPIMISC[GPIO] has had an input change. Only detected if INTENSET has configured this bit to interrupt. Write 1 to clear.
Sourcepub const fn inrst(&self) -> bool
pub const fn inrst(&self) -> bool
Bus Reset. Encodings: 0: Bus not in reset; 1: Bus is in reset
Sourcepub const fn set_inrst(&mut self, val: bool)
pub const fn set_inrst(&mut self, val: bool)
Bus Reset. Encodings: 0: Bus not in reset; 1: Bus is in reset
Sourcepub const fn comppend(&self) -> bool
pub const fn comppend(&self) -> bool
Completion Pending. Encodings: 0: No completions pending; 1: Completions are pending for eSPI. Indicates quiet mode for LPC
Sourcepub const fn set_comppend(&mut self, val: bool)
pub const fn set_comppend(&mut self, val: bool)
Completion Pending. Encodings: 0: No completions pending; 1: Completions are pending for eSPI. Indicates quiet mode for LPC
Sourcepub const fn mastpend(&self) -> bool
pub const fn mastpend(&self) -> bool
Master Pending. Encodings: 0: No mastering pending; 1: Mastering is pending (flash or memory)
Sourcepub const fn set_mastpend(&mut self, val: bool)
pub const fn set_mastpend(&mut self, val: bool)
Master Pending. Encodings: 0: No mastering pending; 1: Mastering is pending (flash or memory)
Sourcepub const fn alertpend(&self) -> bool
pub const fn alertpend(&self) -> bool
Alert Pending. Encodings: 0: No alert request pending; 1: Alert request pin is pending, whether a separate pin or master-in slave-out (MISO). For LPC, indicates that SERIRQ is in process.
Sourcepub const fn set_alertpend(&mut self, val: bool)
pub const fn set_alertpend(&mut self, val: bool)
Alert Pending. Encodings: 0: No alert request pending; 1: Alert request pin is pending, whether a separate pin or master-in slave-out (MISO). For LPC, indicates that SERIRQ is in process.