#[repr(transparent)]pub struct Mctrl(pub u32);Expand description
Master Control. ENABLE may transition only 0->1/2 or 1/2->0; never directly between active modes or to 3. PENA is a five-port independent enable mask, valid only after port TYPE/configuration is set.
Tuple Fields§
§0: u32Implementations§
Source§impl Mctrl
impl Mctrl
Sourcepub const fn enable(&self) -> MctrlEnable
pub const fn enable(&self) -> MctrlEnable
Enable. Encodings: 0: Disabled. Block is not operational.; 1: eSPI (Enhanced Serial Peripheral Interface); 2: LPC (Low Pin Count)
Sourcepub const fn set_enable(&mut self, val: MctrlEnable)
pub const fn set_enable(&mut self, val: MctrlEnable)
Enable. Encodings: 0: Disabled. Block is not operational.; 1: eSPI (Enhanced Serial Peripheral Interface); 2: LPC (Low Pin Count)
Sourcepub const fn rtc_int_bmc(&self) -> bool
pub const fn rtc_int_bmc(&self) -> bool
RTC-Integrated-BMC. Encodings: 0: BMC does not support an integrated RTC.; 1: BMC supports an integrated RTC to which eSPI controller can forward RTC targeting IO cycles. (ESPI slave regs: 0x8, bit 29).
Sourcepub const fn set_rtc_int_bmc(&mut self, val: bool)
pub const fn set_rtc_int_bmc(&mut self, val: bool)
RTC-Integrated-BMC. Encodings: 0: BMC does not support an integrated RTC.; 1: BMC supports an integrated RTC to which eSPI controller can forward RTC targeting IO cycles. (ESPI slave regs: 0x8, bit 29).
Sourcepub const fn pena(&self) -> u8
pub const fn pena(&self) -> u8
Independent enable bits for ports 0..4; configure each port before setting its bit.
Sourcepub const fn set_pena(&mut self, val: u8)
pub const fn set_pena(&mut self, val: u8)
Independent enable bits for ports 0..4; configure each port before setting its bit.
Sourcepub const fn set_p80ena(&mut self, val: bool)
pub const fn set_p80ena(&mut self, val: bool)
Port 80 Enable
Sourcepub const fn set_sblkena(&mut self, val: bool)
pub const fn set_sblkena(&mut self, val: bool)
Status Block Enable
Sourcepub const fn clk_div_disable(&self) -> bool
pub const fn clk_div_disable(&self) -> bool
Clock Division Disable. Encodings: 0: Clock division is enabled.; 1: Clock division is disabled.
Sourcepub const fn set_clk_div_disable(&mut self, val: bool)
pub const fn set_clk_div_disable(&mut self, val: bool)
Clock Division Disable. Encodings: 0: Clock division is enabled.; 1: Clock division is disabled.
Sourcepub const fn early_sample(&self) -> bool
pub const fn early_sample(&self) -> bool
Early Sample
Sourcepub const fn set_early_sample(&mut self, val: bool)
pub const fn set_early_sample(&mut self, val: bool)
Early Sample