Struct Dma1ReqEnable3Clr 

#[repr(transparent)]
pub struct Dma1ReqEnable3Clr(pub u32);

DMA1 Request Enable3

Tuple Fields

0: u32

Implementations

impl Dma1ReqEnable3Clr

pub const fn req96_en1(&self) -> bool

Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req96_en1(&mut self, val: bool)

Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req97_en1(&self) -> bool

Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req97_en1(&mut self, val: bool)

Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req98_en1(&self) -> bool

Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req98_en1(&mut self, val: bool)

Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req99_en1(&self) -> bool

Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req99_en1(&mut self, val: bool)

Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req100_en1(&self) -> bool

Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req100_en1(&mut self, val: bool)

Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req101_en1(&self) -> bool

Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req101_en1(&mut self, val: bool)

Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req102_en1(&self) -> bool

Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req102_en1(&mut self, val: bool)

Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req103_en1(&self) -> bool

Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req103_en1(&mut self, val: bool)

Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req104_en1(&self) -> bool

Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req104_en1(&mut self, val: bool)

Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req105_en1(&self) -> bool

Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req105_en1(&mut self, val: bool)

Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req106_en1(&self) -> bool

Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req106_en1(&mut self, val: bool)

Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req107_en1(&self) -> bool

Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req107_en1(&mut self, val: bool)

Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req108_en1(&self) -> bool

Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req108_en1(&mut self, val: bool)

Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req109_en1(&self) -> bool

Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req109_en1(&mut self, val: bool)

Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req110_en1(&self) -> bool

Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req110_en1(&mut self, val: bool)

Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req111_en1(&self) -> bool

Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req111_en1(&mut self, val: bool)

Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req112_en1(&self) -> bool

Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req112_en1(&mut self, val: bool)

Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req113_en1(&self) -> bool

Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req113_en1(&mut self, val: bool)

Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req114_en1(&self) -> bool

Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req114_en1(&mut self, val: bool)

Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req115_en1(&self) -> bool

Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req115_en1(&mut self, val: bool)

Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req116_en1(&self) -> bool

Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req116_en1(&mut self, val: bool)

Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req117_en1(&self) -> bool

Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req117_en1(&mut self, val: bool)

Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req118_en1(&self) -> bool

Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req118_en1(&mut self, val: bool)

Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req119_en1(&self) -> bool

Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req119_en1(&mut self, val: bool)

Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req120_en1(&self) -> bool

Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn set_req120_en1(&mut self, val: bool)

Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3

pub const fn req121_en1(&self) -> bool

Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3.

pub const fn set_req121_en1(&mut self, val: bool)

Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3.

Trait Implementations

impl Clone for Dma1ReqEnable3Clr

fn clone(&self) -> Dma1ReqEnable3Clr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dma1ReqEnable3Clr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Dma1ReqEnable3Clr

fn default() -> Dma1ReqEnable3Clr

Returns the “default value” for a type.

impl PartialEq for Dma1ReqEnable3Clr

fn eq(&self, other: &Dma1ReqEnable3Clr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dma1ReqEnable3Clr

impl Eq for Dma1ReqEnable3Clr

impl StructuralPartialEq for Dma1ReqEnable3Clr