Struct Inputmux0 

pub struct Inputmux0 { /* private fields */ }

INPUTMUX

Implementations

impl Inputmux0

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn qdcn(self, n: usize) -> Qdcn

Array of registers: QDC_TRIG, QDC_HOME, QDC_INDEX, QDC_PHASEB, QDC_PHASEA

pub const fn sct0_inmux(self, n: usize) -> Reg<Sct0Inmux, RW>

Inputmux Register for SCT0 Input

pub const fn ctimer0cap0(self) -> Reg<Ctimer0cap0, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer0cap1(self) -> Reg<Ctimer0cap1, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer0cap2(self) -> Reg<Ctimer0cap2, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer0cap3(self) -> Reg<Ctimer0cap3, RW>

Capture Select Register for CTIMER Inputs

pub const fn timer0trig(self) -> Reg<Timer0trig, RW>

Trigger Register for CTIMER

pub const fn ctimer1cap0(self) -> Reg<Ctimer1cap0, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer1cap1(self) -> Reg<Ctimer1cap1, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer1cap2(self) -> Reg<Ctimer1cap2, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer1cap3(self) -> Reg<Ctimer1cap3, RW>

Capture Select Register for CTIMER Inputs

pub const fn timer1trig(self) -> Reg<Timer1trig, RW>

Trigger Register for CTIMER

pub const fn ctimer2cap0(self) -> Reg<Ctimer2cap0, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer2cap1(self) -> Reg<Ctimer2cap1, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer2cap2(self) -> Reg<Ctimer2cap2, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer2cap3(self) -> Reg<Ctimer2cap3, RW>

Capture Select Register for CTIMER Inputs

pub const fn timer2trig(self) -> Reg<Timer2trig, RW>

Trigger Register for CTIMER

pub const fn smartdmaarchb_inmux(self, n: usize) -> Reg<SmartdmaarchbInmux, RW>

Inputmux Register for SMARTDMA Arch B Inputs

pub const fn pintsel(self, n: usize) -> Reg<Pintsel, RW>

Pin Interrupt Select

pub const fn freqmeas_ref(self) -> Reg<FreqmeasRef, RW>

Selection for Frequency Measurement Reference Clock

pub const fn freqmeas_tar(self) -> Reg<FreqmeasTar, RW>

Selection for Frequency Measurement Target Clock

pub const fn ctimer3cap0(self) -> Reg<Ctimer3cap0, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer3cap1(self) -> Reg<Ctimer3cap1, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer3cap2(self) -> Reg<Ctimer3cap2, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer3cap3(self) -> Reg<Ctimer3cap3, RW>

Capture Select Register for CTIMER Inputs

pub const fn timer3trig(self) -> Reg<Timer3trig, RW>

Trigger Register for CTIMER

pub const fn ctimer4cap0(self) -> Reg<Ctimer4cap0, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer4cap1(self) -> Reg<Ctimer4cap1, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer4cap2(self) -> Reg<Ctimer4cap2, RW>

Capture Select Register for CTIMER Inputs

pub const fn ctimer4cap3(self) -> Reg<Ctimer4cap3, RW>

Capture Select Register for CTIMER Inputs

pub const fn timer4trig(self) -> Reg<Timer4trig, RW>

Trigger Register for CTIMER

pub const fn cmp0_trig(self) -> Reg<Cmp0Trig, RW>

CMP0 Input Connections

pub const fn adc0_trig(self, n: usize) -> Reg<Adc0Trig, RW>

ADC Trigger Input Connections

pub const fn adc1_trig(self, n: usize) -> Reg<Adc1Trig, RW>

ADC Trigger Input Connections

pub const fn dac0_trig(self) -> Reg<Dac0Trig, RW>

DAC0 Trigger Inputs

pub const fn dac1_trig(self) -> Reg<Dac1Trig, RW>

DAC1 Trigger Inputs

pub const fn dac2_trig(self) -> Reg<Dac2Trig, RW>

DAC2 Trigger Inputs

pub const fn flex_pwm0_sm_extsync(self, n: usize) -> Reg<FlexPwm0SmExtsync, RW>

PWM0 External Synchronization

pub const fn flex_pwm0_sm_exta(self, n: usize) -> Reg<FlexPwm0SmExta, RW>

PWM0 Input Trigger Connections

pub const fn flex_pwm0_extforce(self) -> Reg<FlexPwm0Extforce, RW>

PWM0 External Force Trigger Connections

pub const fn flex_pwm0_fault(self, n: usize) -> Reg<FlexPwm0Fault, RW>

PWM0 Fault Input Trigger Connections

pub const fn flex_pwm1_sm_extsync(self, n: usize) -> Reg<FlexPwm1SmExtsync, RW>

PWM1 External Synchronization

pub const fn flex_pwm1_sm_exta(self, n: usize) -> Reg<FlexPwm1SmExta, RW>

PWM1 Input EXTA Connections

pub const fn flex_pwm1_extforce(self) -> Reg<FlexPwm1Extforce, RW>

PWM1 External Force Trigger Connections

pub const fn flex_pwm1_fault(self, n: usize) -> Reg<FlexPwm1Fault, RW>

PWM1 Fault Input Trigger Connections

pub const fn pwm0_ext_clk(self) -> Reg<Pwm0ExtClk, RW>

PWM0 External Clock Trigger

pub const fn pwm1_ext_clk(self) -> Reg<Pwm1ExtClk, RW>

PWM1 External Clock Trigger

pub const fn evtg_trig(self, n: usize) -> Reg<EvtgTrig, RW>

EVTG Trigger Input Connections

pub const fn usbfs_trig(self) -> Reg<UsbfsTrig, RW>

USB-FS Trigger Input Connections

pub const fn tsi_trig(self) -> Reg<TsiTrig, RW>

TSI Trigger Input Connections

pub const fn ext_trig(self, n: usize) -> Reg<ExtTrig, RW>

EXT Trigger Connections

pub const fn cmp1_trig(self) -> Reg<Cmp1Trig, RW>

CMP1 Input Connections

pub const fn cmp2_trig(self) -> Reg<Cmp2Trig, RW>

CMP2 Input Connections

pub const fn sinc_filter_ch(self, n: usize) -> Reg<SincFilterCh, RW>

SINC Filter Channel Trigger Input Connections

pub const fn opamp_trig(self, n: usize) -> Reg<OpampTrig, RW>

OPAMP Trigger Input Connections

pub const fn flexcomm0_trig(self) -> Reg<Flexcomm0Trig, RW>

LP_FLEXCOMM0 Trigger Input Connections

pub const fn flexcomm1_trig(self) -> Reg<Flexcomm1Trig, RW>

LP_FLEXCOMM1 Trigger Input Connections

pub const fn flexcomm2_trig(self) -> Reg<Flexcomm2Trig, RW>

LP_FLEXCOMM2 Trigger Input Connections

pub const fn flexcomm3_trig(self) -> Reg<Flexcomm3Trig, RW>

LP_FLEXCOMM3 Trigger Input Connections

pub const fn flexcomm4_trig(self) -> Reg<Flexcomm4Trig, RW>

LP_FLEXCOMM4 Trigger Input Connections

pub const fn flexcomm5_trig(self) -> Reg<Flexcomm5Trig, RW>

LP_FLEXCOMM5 Trigger Input Connections

pub const fn flexcomm6_trig(self) -> Reg<Flexcomm6Trig, RW>

LP_FLEXCOMM6 Trigger Input Connections

pub const fn flexcomm7_trig(self) -> Reg<Flexcomm7Trig, RW>

LP_FLEXCOMM7 Trigger Input Connections

pub const fn flexcomm8_trig(self) -> Reg<Flexcomm8Trig, RW>

LP_FLEXCOMM8 Trigger Input Connections

pub const fn flexcomm9_trig(self) -> Reg<Flexcomm9Trig, RW>

LP_FLEXCOMM9 Trigger Input Connections

pub const fn flexio_trig(self, n: usize) -> Reg<FlexioTrig, RW>

FlexIO Trigger Input Connections

pub const fn dma0_req_enable0(self) -> Reg<Dma0ReqEnable0, RW>

DMA0 Request Enable0

pub const fn dma0_req_enable0_set(self) -> Reg<Dma0ReqEnable0Set, W>

DMA0 Request Enable0

pub const fn dma0_req_enable0_clr(self) -> Reg<Dma0ReqEnable0Clr, W>

DMA0 Request Enable0

pub const fn dma0_req_enable0_tog(self) -> Reg<Dma0ReqEnable0Tog, W>

DMA0 Request Enable0

pub const fn dma0_req_enable1(self) -> Reg<Dma0ReqEnable1, RW>

DMA0 Request Enable1

pub const fn dma0_req_enable1_set(self) -> Reg<Dma0ReqEnable1Set, W>

DMA0 Request Enable1

pub const fn dma0_req_enable1_clr(self) -> Reg<Dma0ReqEnable1Clr, W>

DMA0 Request Enable1

pub const fn dma0_req_enable1_tog(self) -> Reg<Dma0ReqEnable1Tog, W>

DMA0 Request Enable1

pub const fn dma0_req_enable2(self) -> Reg<Dma0ReqEnable2, RW>

DMA0 Request Enable2

pub const fn dma0_req_enable2_set(self) -> Reg<Dma0ReqEnable2Set, W>

DMA0 Request Enable2

pub const fn dma0_req_enable2_clr(self) -> Reg<Dma0ReqEnable2Clr, W>

DMA0 Request Enable2

pub const fn dma0_req_enable2_tog(self) -> Reg<Dma0ReqEnable2Tog, W>

DMA0 Request Enable2

pub const fn dma0_req_enable3(self) -> Reg<Dma0ReqEnable3, RW>

DMA0 Request Enable3

pub const fn dma0_req_enable3_set(self) -> Reg<Dma0ReqEnable3Set, W>

DMA0 Request Enable3

pub const fn dma0_req_enable3_clr(self) -> Reg<Dma0ReqEnable3Clr, W>

DMA0 Request Enable3

pub const fn dma1_req_enable0(self) -> Reg<Dma1ReqEnable0, RW>

DMA1 Request Enable0

pub const fn dma1_req_enable0_set(self) -> Reg<Dma1ReqEnable0Set, W>

DMA1 Request Enable0

pub const fn dma1_req_enable0_clr(self) -> Reg<Dma1ReqEnable0Clr, W>

DMA1 Request Enable0

pub const fn dma1_req_enable0_tog(self) -> Reg<Dma1ReqEnable0Tog, W>

DMA1 Request Enable0

pub const fn dma1_req_enable1(self) -> Reg<Dma1ReqEnable1, RW>

DMA1 Request Enable1

pub const fn dma1_req_enable1_set(self) -> Reg<Dma1ReqEnable1Set, W>

DMA1 Request Enable1

pub const fn dma1_req_enable1_clr(self) -> Reg<Dma1ReqEnable1Clr, W>

DMA1 Request Enable1

pub const fn dma1_req_enable1_tog(self) -> Reg<Dma1ReqEnable1Tog, W>

DMA1 Request Enable1

pub const fn dma1_req_enable2(self) -> Reg<Dma1ReqEnable2, RW>

DMA1 Request Enable2

pub const fn dma1_req_enable2_set(self) -> Reg<Dma1ReqEnable2Set, W>

DMA1 Request Enable2

pub const fn dma1_req_enable2_clr(self) -> Reg<Dma1ReqEnable2Clr, W>

DMA1 Request Enable2

pub const fn dma1_req_enable2_tog(self) -> Reg<Dma1ReqEnable2Tog, W>

DMA1 Request Enable2

pub const fn dma1_req_enable3(self) -> Reg<Dma1ReqEnable3, RW>

DMA1 Request Enable3

pub const fn dma1_req_enable3_set(self) -> Reg<Dma1ReqEnable3Set, W>

DMA1 Request Enable3

pub const fn dma1_req_enable3_clr(self) -> Reg<Dma1ReqEnable3Clr, W>

DMA1 Request Enable3

Trait Implementations

impl Clone for Inputmux0

fn clone(&self) -> Inputmux0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Inputmux0

fn eq(&self, other: &Inputmux0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Inputmux0

impl Eq for Inputmux0

impl Send for Inputmux0

impl StructuralPartialEq for Inputmux0

impl Sync for Inputmux0