pub struct AhbSecureCtrl { /* private fields */ }Expand description
LPC_Next0 AHB secure controller
Implementations§
Source§impl AhbSecureCtrl
impl AhbSecureCtrl
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
Sourcepub const fn rom_mem_rule(self, n: usize) -> Reg<RomMemRule, RW>
pub const fn rom_mem_rule(self, n: usize) -> Reg<RomMemRule, RW>
Memory ROM Rule(n) Register
Sourcepub const fn flexspi0_region0_rule(
self,
n: usize,
) -> Reg<Flexspi0Region0Rule, RW>
pub const fn flexspi0_region0_rule( self, n: usize, ) -> Reg<Flexspi0Region0Rule, RW>
FLEXSPI0 Region 0 Rule(n) Register
Sourcepub const fn flexspi0_region1_rule0(self) -> Reg<Flexspi0Region1Rule0, RW>
pub const fn flexspi0_region1_rule0(self) -> Reg<Flexspi0Region1Rule0, RW>
FLEXSPI0 Region 1 Rule 0 Register
Sourcepub const fn flexspi0_region2_rule0(self) -> Reg<Flexspi0Region2Rule0, RW>
pub const fn flexspi0_region2_rule0(self) -> Reg<Flexspi0Region2Rule0, RW>
FLEXSPI0 Region 2 Rule 0 Register
Sourcepub const fn flexspi0_region3_rule0(self) -> Reg<Flexspi0Region3Rule0, RW>
pub const fn flexspi0_region3_rule0(self) -> Reg<Flexspi0Region3Rule0, RW>
FLEXSPI0 Region 3 Rule 0 Register
Sourcepub const fn flexspi0_region4_rule0(self) -> Reg<Flexspi0Region4Rule0, RW>
pub const fn flexspi0_region4_rule0(self) -> Reg<Flexspi0Region4Rule0, RW>
FLEXSPI0 Region 4 Rule 0 Register
Sourcepub const fn ram00_rule(self, n: usize) -> Reg<Ram00Rule, RW>
pub const fn ram00_rule(self, n: usize) -> Reg<Ram00Rule, RW>
SRAM Partition 00 Rule(n) Register
Sourcepub const fn ram01_rule(self, n: usize) -> Reg<Ram01Rule, RW>
pub const fn ram01_rule(self, n: usize) -> Reg<Ram01Rule, RW>
SRAM Partition 01 Rule(n) Register
Sourcepub const fn ram02_rule(self, n: usize) -> Reg<Ram02Rule, RW>
pub const fn ram02_rule(self, n: usize) -> Reg<Ram02Rule, RW>
SRAM Partition 02 Rule(n) Register
Sourcepub const fn ram03_rule(self, n: usize) -> Reg<Ram03Rule, RW>
pub const fn ram03_rule(self, n: usize) -> Reg<Ram03Rule, RW>
SRAM Partition 03 Rule(n) Register
Sourcepub const fn ram04_rule(self, n: usize) -> Reg<Ram04Rule, RW>
pub const fn ram04_rule(self, n: usize) -> Reg<Ram04Rule, RW>
SRAM Partition 04 Rule(n) Register
Sourcepub const fn ram05_rule(self, n: usize) -> Reg<Ram05Rule, RW>
pub const fn ram05_rule(self, n: usize) -> Reg<Ram05Rule, RW>
SRAM Partition 05 Rule(n) Register
Sourcepub const fn ram06_rule(self, n: usize) -> Reg<Ram06Rule, RW>
pub const fn ram06_rule(self, n: usize) -> Reg<Ram06Rule, RW>
SRAM Partition 06 Rule(n) Register
Sourcepub const fn ram07_rule(self, n: usize) -> Reg<Ram07Rule, RW>
pub const fn ram07_rule(self, n: usize) -> Reg<Ram07Rule, RW>
SRAM Partition 07 Rule(n) Register
Sourcepub const fn ram08_rule(self, n: usize) -> Reg<Ram08Rule, RW>
pub const fn ram08_rule(self, n: usize) -> Reg<Ram08Rule, RW>
SRAM Partition 08 Rule(n) Register
Sourcepub const fn ram09_rule(self, n: usize) -> Reg<Ram09Rule, RW>
pub const fn ram09_rule(self, n: usize) -> Reg<Ram09Rule, RW>
SRAM Partition 09 Rule(n) Register
Sourcepub const fn ram10_rule(self, n: usize) -> Reg<Ram10Rule, RW>
pub const fn ram10_rule(self, n: usize) -> Reg<Ram10Rule, RW>
SRAM Partition 10 Rule(n) Register
Sourcepub const fn ram11_rule(self, n: usize) -> Reg<Ram11Rule, RW>
pub const fn ram11_rule(self, n: usize) -> Reg<Ram11Rule, RW>
SRAM Partition 11 Rule(n) Register
Sourcepub const fn ram12_rule(self, n: usize) -> Reg<Ram12Rule, RW>
pub const fn ram12_rule(self, n: usize) -> Reg<Ram12Rule, RW>
SRAM Partition 12 Rule(n) Register
Sourcepub const fn ram13_rule(self, n: usize) -> Reg<Ram13Rule, RW>
pub const fn ram13_rule(self, n: usize) -> Reg<Ram13Rule, RW>
SRAM Partition 13 Rule(n) Register
Sourcepub const fn ram14_rule(self, n: usize) -> Reg<Ram14Rule, RW>
pub const fn ram14_rule(self, n: usize) -> Reg<Ram14Rule, RW>
SRAM Partition 14 Rule(n) Register
Sourcepub const fn ram15_rule(self, n: usize) -> Reg<Ram15Rule, RW>
pub const fn ram15_rule(self, n: usize) -> Reg<Ram15Rule, RW>
SRAM Partition 15 Rule(n) Register
Sourcepub const fn ram16_rule(self, n: usize) -> Reg<Ram16Rule, RW>
pub const fn ram16_rule(self, n: usize) -> Reg<Ram16Rule, RW>
SRAM Partition 16 Rule(n) Register
Sourcepub const fn ram17_rule(self, n: usize) -> Reg<Ram17Rule, RW>
pub const fn ram17_rule(self, n: usize) -> Reg<Ram17Rule, RW>
SRAM Partition 17 Rule(n) Register
Sourcepub const fn ram18_rule(self, n: usize) -> Reg<Ram18Rule, RW>
pub const fn ram18_rule(self, n: usize) -> Reg<Ram18Rule, RW>
SRAM Partition 18 Rule(n) Register
Sourcepub const fn ram19_rule(self, n: usize) -> Reg<Ram19Rule, RW>
pub const fn ram19_rule(self, n: usize) -> Reg<Ram19Rule, RW>
SRAM Partition 19 Rule(n) Register
Sourcepub const fn ram20_rule(self, n: usize) -> Reg<Ram20Rule, RW>
pub const fn ram20_rule(self, n: usize) -> Reg<Ram20Rule, RW>
SRAM Partition 20 Rule(n) Register
Sourcepub const fn ram21_rule(self, n: usize) -> Reg<Ram21Rule, RW>
pub const fn ram21_rule(self, n: usize) -> Reg<Ram21Rule, RW>
SRAM Partition 21 Rule(n) Register
Sourcepub const fn ram22_rule(self, n: usize) -> Reg<Ram22Rule, RW>
pub const fn ram22_rule(self, n: usize) -> Reg<Ram22Rule, RW>
SRAM Partition 22 Rule(n) Register
Sourcepub const fn ram23_rule(self, n: usize) -> Reg<Ram23Rule, RW>
pub const fn ram23_rule(self, n: usize) -> Reg<Ram23Rule, RW>
SRAM Partition 23 Rule(n) Register
Sourcepub const fn ram24_rule(self, n: usize) -> Reg<Ram24Rule, RW>
pub const fn ram24_rule(self, n: usize) -> Reg<Ram24Rule, RW>
SRAM Partition 24 Rule(n) Register
Sourcepub const fn ram25_rule(self, n: usize) -> Reg<Ram25Rule, RW>
pub const fn ram25_rule(self, n: usize) -> Reg<Ram25Rule, RW>
SRAM Partition 25 Rule(n) Register
Sourcepub const fn ram26_rule(self, n: usize) -> Reg<Ram26Rule, RW>
pub const fn ram26_rule(self, n: usize) -> Reg<Ram26Rule, RW>
SRAM Partition 26 Rule(n) Register
Sourcepub const fn ram27_rule(self, n: usize) -> Reg<Ram27Rule, RW>
pub const fn ram27_rule(self, n: usize) -> Reg<Ram27Rule, RW>
SRAM Partition 27 Rule(n) Register
Sourcepub const fn ram28_rule(self, n: usize) -> Reg<Ram28Rule, RW>
pub const fn ram28_rule(self, n: usize) -> Reg<Ram28Rule, RW>
SRAM Partition 28 Rule(n) Register
Sourcepub const fn ram29_rule(self, n: usize) -> Reg<Ram29Rule, RW>
pub const fn ram29_rule(self, n: usize) -> Reg<Ram29Rule, RW>
SRAM Partition 29 Rule(n) Register
Sourcepub const fn pif_hifi4_x_mem_rule0(self) -> Reg<PifHifi4XMemRule0, RW>
pub const fn pif_hifi4_x_mem_rule0(self) -> Reg<PifHifi4XMemRule0, RW>
Security access rules for HiFi 4 memory sectors (0x24000000–0x240FFFFF). Each sector is 32 Kbytes, there’re 4 sectors in total.
Sourcepub const fn apb_grp0_mem_rule0(self) -> Reg<ApbGrp0MemRule0, RW>
pub const fn apb_grp0_mem_rule0(self) -> Reg<ApbGrp0MemRule0, RW>
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn apb_grp0_mem_rule1(self) -> Reg<ApbGrp0MemRule1, RW>
pub const fn apb_grp0_mem_rule1(self) -> Reg<ApbGrp0MemRule1, RW>
Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn apb_grp1_mem_rule0(self) -> Reg<ApbGrp1MemRule0, RW>
pub const fn apb_grp1_mem_rule0(self) -> Reg<ApbGrp1MemRule0, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn apb_grp1_mem_rule1(self) -> Reg<ApbGrp1MemRule1, RW>
pub const fn apb_grp1_mem_rule1(self) -> Reg<ApbGrp1MemRule1, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn apb_grp1_mem_rule2(self) -> Reg<ApbGrp1MemRule2, RW>
pub const fn apb_grp1_mem_rule2(self) -> Reg<ApbGrp1MemRule2, RW>
Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn ahb_periph0_slave_rule0(self) -> Reg<AhbPeriph0SlaveRule0, RW>
pub const fn ahb_periph0_slave_rule0(self) -> Reg<AhbPeriph0SlaveRule0, RW>
Security access rules for AHB peripheral slaves area 0x40100000–0x4010FFFF
Sourcepub const fn aips_bridge0_mem_rule0(self) -> Reg<AipsBridge0MemRule0, RW>
pub const fn aips_bridge0_mem_rule0(self) -> Reg<AipsBridge0MemRule0, RW>
0x40110000–0x4011FFFF
Sourcepub const fn ahb_periph1_slave_rule0(self) -> Reg<AhbPeriph1SlaveRule0, RW>
pub const fn ahb_periph1_slave_rule0(self) -> Reg<AhbPeriph1SlaveRule0, RW>
the memory map is 0x40120000–0x40127FFF
Sourcepub const fn aips_bridge1_mem_rule0(self) -> Reg<AipsBridge1MemRule0, RW>
pub const fn aips_bridge1_mem_rule0(self) -> Reg<AipsBridge1MemRule0, RW>
Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn aips_bridge1_mem_rule1(self) -> Reg<AipsBridge1MemRule1, RW>
pub const fn aips_bridge1_mem_rule1(self) -> Reg<AipsBridge1MemRule1, RW>
Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there’re 16 sectors in total.
Sourcepub const fn ahb_periph2_slave_rule0(self) -> Reg<AhbPeriph2SlaveRule0, RW>
pub const fn ahb_periph2_slave_rule0(self) -> Reg<AhbPeriph2SlaveRule0, RW>
Security access rules for AHB peripheral slaves area 0x40140000–0x4014BFFF
Sourcepub const fn security_ctrl_mem_rule0(self) -> Reg<SecurityCtrlMemRule0, RW>
pub const fn security_ctrl_mem_rule0(self) -> Reg<SecurityCtrlMemRule0, RW>
0x40148000–0x4014BFFF
Sourcepub const fn ahb_periph3_slave_rule0(self) -> Reg<AhbPeriph3SlaveRule0, RW>
pub const fn ahb_periph3_slave_rule0(self) -> Reg<AhbPeriph3SlaveRule0, RW>
Security access rules for AHB peripheral slaves area 0x40150000–0x40158FFF
Sourcepub const fn sec_vio_addr(self, n: usize) -> Reg<SecVioAddr, R>
pub const fn sec_vio_addr(self, n: usize) -> Reg<SecVioAddr, R>
most recent security violation address for AHB layer n
Sourcepub const fn sec_vio_misc_info(self, n: usize) -> Reg<SecVioMiscInfo, R>
pub const fn sec_vio_misc_info(self, n: usize) -> Reg<SecVioMiscInfo, R>
most recent security violation miscellaneous information for AHB layer n
Sourcepub const fn sec_vio_info_valid(self) -> Reg<SecVioInfoValid, RW>
pub const fn sec_vio_info_valid(self) -> Reg<SecVioInfoValid, RW>
security violation address/information registers valid flags
Sourcepub const fn sec_gpio_mask0(self) -> Reg<SecGpioMask0, RW>
pub const fn sec_gpio_mask0(self) -> Reg<SecGpioMask0, RW>
Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world.
Sourcepub const fn sec_gpio_mask1(self) -> Reg<SecGpioMask1, RW>
pub const fn sec_gpio_mask1(self) -> Reg<SecGpioMask1, RW>
Secure GPIO mask for port 1 pins.
Sourcepub const fn sec_gpio_mask2(self) -> Reg<SecGpioMask2, RW>
pub const fn sec_gpio_mask2(self) -> Reg<SecGpioMask2, RW>
Secure GPIO mask for port 2 pins.
Sourcepub const fn sec_gpio_mask3(self) -> Reg<SecGpioMask3, RW>
pub const fn sec_gpio_mask3(self) -> Reg<SecGpioMask3, RW>
Secure GPIO mask for port 3 pins.
Sourcepub const fn sec_gpio_mask4(self) -> Reg<SecGpioMask4, RW>
pub const fn sec_gpio_mask4(self) -> Reg<SecGpioMask4, RW>
Secure GPIO mask for port 4 pins.
Sourcepub const fn sec_gpio_mask5(self) -> Reg<SecGpioMask5, RW>
pub const fn sec_gpio_mask5(self) -> Reg<SecGpioMask5, RW>
Secure GPIO mask for port 5 pins.
Sourcepub const fn sec_gpio_mask6(self) -> Reg<SecGpioMask6, RW>
pub const fn sec_gpio_mask6(self) -> Reg<SecGpioMask6, RW>
Secure GPIO mask for port 6 pins.
Sourcepub const fn sec_gpio_mask7(self) -> Reg<SecGpioMask7, RW>
pub const fn sec_gpio_mask7(self) -> Reg<SecGpioMask7, RW>
Secure GPIO mask for port 7 pins.
Sourcepub const fn sec_dsp_int_mask(self) -> Reg<SecDspIntMask, RW>
pub const fn sec_dsp_int_mask(self) -> Reg<SecDspIntMask, RW>
secure general purpose register 8 used to mask interrupts to DSP for security purpose
Sourcepub const fn sec_mask_lock(self) -> Reg<SecMaskLock, RW>
pub const fn sec_mask_lock(self) -> Reg<SecMaskLock, RW>
sec_gp_reg write-lock bits
Sourcepub const fn master_sec_level(self) -> Reg<MasterSecLevel, RW>
pub const fn master_sec_level(self) -> Reg<MasterSecLevel, RW>
master secure level register
Sourcepub const fn master_sec_level_anti_pol(self) -> Reg<MasterSecLevelAntiPol, RW>
pub const fn master_sec_level_anti_pol(self) -> Reg<MasterSecLevelAntiPol, RW>
master secure level anti-pole register
Sourcepub const fn cm33_lock_reg(self) -> Reg<Cm33LockReg, RW>
pub const fn cm33_lock_reg(self) -> Reg<Cm33LockReg, RW>
m33 lock control register
Sourcepub const fn misc_ctrl_dp_reg(self) -> Reg<MiscCtrlDpReg, RW>
pub const fn misc_ctrl_dp_reg(self) -> Reg<MiscCtrlDpReg, RW>
secure control duplicate register
Sourcepub const fn misc_ctrl_reg(self) -> Reg<MiscCtrlReg, RW>
pub const fn misc_ctrl_reg(self) -> Reg<MiscCtrlReg, RW>
secure control register
Trait Implementations§
Source§impl Clone for AhbSecureCtrl
impl Clone for AhbSecureCtrl
Source§fn clone(&self) -> AhbSecureCtrl
fn clone(&self) -> AhbSecureCtrl
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more