Enum Interrupt
pub enum Interrupt {
Show 79 variants
WWDG = 0,
PWR_PVD = 1,
RTC = 2,
TAMP = 3,
RAMCFG = 4,
FLASH = 5,
RCC = 6,
EXTI0 = 7,
EXTI1 = 8,
EXTI2 = 9,
EXTI3 = 10,
EXTI4 = 11,
EXTI5 = 12,
EXTI6 = 13,
EXTI7 = 14,
EXTI8 = 15,
EXTI9 = 16,
EXTI10 = 17,
EXTI11 = 18,
EXTI12 = 19,
EXTI13 = 20,
EXTI14 = 21,
EXTI15 = 22,
LPDMA1_CH0 = 23,
LPDMA1_CH1 = 24,
LPDMA1_CH2 = 25,
LPDMA1_CH3 = 26,
LPDMA1_CH4 = 27,
LPDMA1_CH5 = 28,
LPDMA1_CH6 = 29,
LPDMA1_CH7 = 30,
IWDG = 31,
ADC1 = 32,
ADC2 = 33,
TIM1_BRK = 36,
TIM1_UP = 37,
TIM1_TRG_COM = 38,
TIM1_CC = 39,
TIM2 = 40,
TIM5 = 41,
TIM6 = 42,
TIM7 = 43,
I2C1_EV = 44,
I2C1_ERR = 45,
I3C1_EV = 46,
I3C1_ERR = 47,
SPI1 = 48,
SPI2 = 49,
SPI3 = 50,
USART1 = 51,
USART2 = 52,
USART3 = 53,
UART4 = 54,
UART5 = 55,
LPUART1 = 56,
LPTIM1 = 57,
TIM12 = 58,
TIM15 = 59,
TIM16 = 60,
TIM17 = 61,
USB_DRD_FS = 62,
CRS = 63,
RNG = 64,
FPU = 65,
ICACHE = 66,
CORDIC = 67,
HASH = 69,
I2C2_EV = 70,
I2C2_ERR = 71,
TIM8_BRK = 72,
TIM8_UP = 73,
TIM8_TRG_COM = 74,
TIM8_CC = 75,
COMP1 = 76,
DAC1 = 77,
LPDMA2_CH0 = 78,
LPDMA2_CH1 = 79,
LPDMA2_CH2 = 80,
LPDMA2_CH3 = 81,
}Variants§
WWDG = 0
0 - WWDG
PWR_PVD = 1
1 - PWR_PVD
RTC = 2
2 - RTC
TAMP = 3
3 - TAMP
RAMCFG = 4
4 - RAMCFG
FLASH = 5
5 - FLASH
RCC = 6
6 - RCC
EXTI0 = 7
7 - EXTI0
EXTI1 = 8
8 - EXTI1
EXTI2 = 9
9 - EXTI2
EXTI3 = 10
10 - EXTI3
EXTI4 = 11
11 - EXTI4
EXTI5 = 12
12 - EXTI5
EXTI6 = 13
13 - EXTI6
EXTI7 = 14
14 - EXTI7
EXTI8 = 15
15 - EXTI8
EXTI9 = 16
16 - EXTI9
EXTI10 = 17
17 - EXTI10
EXTI11 = 18
18 - EXTI11
EXTI12 = 19
19 - EXTI12
EXTI13 = 20
20 - EXTI13
EXTI14 = 21
21 - EXTI14
EXTI15 = 22
22 - EXTI15
LPDMA1_CH0 = 23
23 - LPDMA1_CH0
LPDMA1_CH1 = 24
24 - LPDMA1_CH1
LPDMA1_CH2 = 25
25 - LPDMA1_CH2
LPDMA1_CH3 = 26
26 - LPDMA1_CH3
LPDMA1_CH4 = 27
27 - LPDMA1_CH4
LPDMA1_CH5 = 28
28 - LPDMA1_CH5
LPDMA1_CH6 = 29
29 - LPDMA1_CH6
LPDMA1_CH7 = 30
30 - LPDMA1_CH7
IWDG = 31
31 - IWDG
ADC1 = 32
32 - ADC1
ADC2 = 33
33 - ADC2
TIM1_BRK = 36
36 - TIM1_BRK
TIM1_UP = 37
37 - TIM1_UP
TIM1_TRG_COM = 38
38 - TIM1_TRG_COM
TIM1_CC = 39
39 - TIM1_CC
TIM2 = 40
40 - TIM2
TIM5 = 41
41 - TIM5
TIM6 = 42
42 - TIM6
TIM7 = 43
43 - TIM7
I2C1_EV = 44
44 - I2C1_EV
I2C1_ERR = 45
45 - I2C1_ERR
I3C1_EV = 46
46 - I3C1_EV
I3C1_ERR = 47
47 - I3C1_ERR
SPI1 = 48
48 - SPI1
SPI2 = 49
49 - SPI2
SPI3 = 50
50 - SPI3
USART1 = 51
51 - USART1
USART2 = 52
52 - USART2
USART3 = 53
53 - USART3
UART4 = 54
54 - UART4
UART5 = 55
55 - UART5
LPUART1 = 56
56 - LPUART1
LPTIM1 = 57
57 - LPTIM1
TIM12 = 58
58 - TIM12
TIM15 = 59
59 - TIM15
TIM16 = 60
60 - TIM16
TIM17 = 61
61 - TIM17
USB_DRD_FS = 62
62 - USB_DRD_FS
CRS = 63
63 - CRS
RNG = 64
64 - RNG
FPU = 65
65 - FPU
ICACHE = 66
66 - ICACHE
CORDIC = 67
67 - CORDIC
HASH = 69
69 - HASH
I2C2_EV = 70
70 - I2C2_EV
I2C2_ERR = 71
71 - I2C2_ERR
TIM8_BRK = 72
72 - TIM8_BRK
TIM8_UP = 73
73 - TIM8_UP
TIM8_TRG_COM = 74
74 - TIM8_TRG_COM
TIM8_CC = 75
75 - TIM8_CC
COMP1 = 76
76 - COMP1
DAC1 = 77
77 - DAC1
LPDMA2_CH0 = 78
78 - LPDMA2_CH0
LPDMA2_CH1 = 79
79 - LPDMA2_CH1
LPDMA2_CH2 = 80
80 - LPDMA2_CH2
LPDMA2_CH3 = 81
81 - LPDMA2_CH3