Enum Interrupt
pub enum Interrupt {
Show 77 variants
WWDG = 0,
PVD = 1,
TAMP_STAMP = 2,
RTC_WKUP = 3,
FLASH = 4,
RCC = 5,
EXTI0 = 6,
EXTI1 = 7,
EXTI2 = 8,
EXTI3 = 9,
EXTI4 = 10,
DMA1_STREAM0 = 11,
DMA1_STREAM1 = 12,
DMA1_STREAM2 = 13,
DMA1_STREAM3 = 14,
DMA1_STREAM4 = 15,
DMA1_STREAM5 = 16,
DMA1_STREAM6 = 17,
ADC = 18,
CAN1_TX = 19,
CAN1_RX0 = 20,
CAN1_RX1 = 21,
CAN1_SCE = 22,
EXTI9_5 = 23,
TIM1_BRK_TIM9 = 24,
TIM1_UP_TIM10 = 25,
TIM1_TRG_COM_TIM11 = 26,
TIM1_CC = 27,
TIM2 = 28,
TIM3 = 29,
TIM4 = 30,
I2C1_EV = 31,
I2C1_ER = 32,
I2C2_EV = 33,
I2C2_ER = 34,
SPI1 = 35,
SPI2 = 36,
USART1 = 37,
USART2 = 38,
USART3 = 39,
EXTI15_10 = 40,
RTC_ALARM = 41,
OTG_FS_WKUP = 42,
TIM8_BRK_TIM12 = 43,
TIM8_UP_TIM13 = 44,
TIM8_TRG_COM_TIM14 = 45,
TIM8_CC = 46,
DMA1_STREAM7 = 47,
SDIO = 49,
TIM5 = 50,
SPI3 = 51,
TIM6 = 54,
TIM7 = 55,
DMA2_STREAM0 = 56,
DMA2_STREAM1 = 57,
DMA2_STREAM2 = 58,
DMA2_STREAM3 = 59,
DMA2_STREAM4 = 60,
DFSDM1_FLT0 = 61,
DFSDM1_FLT1 = 62,
CAN2_TX = 63,
CAN2_RX0 = 64,
CAN2_RX1 = 65,
CAN2_SCE = 66,
OTG_FS = 67,
DMA2_STREAM5 = 68,
DMA2_STREAM6 = 69,
DMA2_STREAM7 = 70,
USART6 = 71,
I2C3_EV = 72,
I2C3_ER = 73,
RNG = 80,
FPU = 81,
SPI4 = 84,
SPI5 = 85,
FMPI2C1_EV = 95,
FMPI2C1_ER = 96,
}
Variants§
WWDG = 0
0 - WWDG
PVD = 1
1 - PVD
TAMP_STAMP = 2
2 - TAMP_STAMP
RTC_WKUP = 3
3 - RTC_WKUP
FLASH = 4
4 - FLASH
RCC = 5
5 - RCC
EXTI0 = 6
6 - EXTI0
EXTI1 = 7
7 - EXTI1
EXTI2 = 8
8 - EXTI2
EXTI3 = 9
9 - EXTI3
EXTI4 = 10
10 - EXTI4
DMA1_STREAM0 = 11
11 - DMA1_STREAM0
DMA1_STREAM1 = 12
12 - DMA1_STREAM1
DMA1_STREAM2 = 13
13 - DMA1_STREAM2
DMA1_STREAM3 = 14
14 - DMA1_STREAM3
DMA1_STREAM4 = 15
15 - DMA1_STREAM4
DMA1_STREAM5 = 16
16 - DMA1_STREAM5
DMA1_STREAM6 = 17
17 - DMA1_STREAM6
ADC = 18
18 - ADC
CAN1_TX = 19
19 - CAN1_TX
CAN1_RX0 = 20
20 - CAN1_RX0
CAN1_RX1 = 21
21 - CAN1_RX1
CAN1_SCE = 22
22 - CAN1_SCE
EXTI9_5 = 23
23 - EXTI9_5
TIM1_BRK_TIM9 = 24
24 - TIM1_BRK_TIM9
TIM1_UP_TIM10 = 25
25 - TIM1_UP_TIM10
TIM1_TRG_COM_TIM11 = 26
26 - TIM1_TRG_COM_TIM11
TIM1_CC = 27
27 - TIM1_CC
TIM2 = 28
28 - TIM2
TIM3 = 29
29 - TIM3
TIM4 = 30
30 - TIM4
I2C1_EV = 31
31 - I2C1_EV
I2C1_ER = 32
32 - I2C1_ER
I2C2_EV = 33
33 - I2C2_EV
I2C2_ER = 34
34 - I2C2_ER
SPI1 = 35
35 - SPI1
SPI2 = 36
36 - SPI2
USART1 = 37
37 - USART1
USART2 = 38
38 - USART2
USART3 = 39
39 - USART3
EXTI15_10 = 40
40 - EXTI15_10
RTC_ALARM = 41
41 - RTC_ALARM
OTG_FS_WKUP = 42
42 - OTG_FS_WKUP
TIM8_BRK_TIM12 = 43
43 - TIM8_BRK_TIM12
TIM8_UP_TIM13 = 44
44 - TIM8_UP_TIM13
TIM8_TRG_COM_TIM14 = 45
45 - TIM8_TRG_COM_TIM14
TIM8_CC = 46
46 - TIM8_CC
DMA1_STREAM7 = 47
47 - DMA1_STREAM7
SDIO = 49
49 - SDIO
TIM5 = 50
50 - TIM5
SPI3 = 51
51 - SPI3
TIM6 = 54
54 - TIM6
TIM7 = 55
55 - TIM7
DMA2_STREAM0 = 56
56 - DMA2_STREAM0
DMA2_STREAM1 = 57
57 - DMA2_STREAM1
DMA2_STREAM2 = 58
58 - DMA2_STREAM2
DMA2_STREAM3 = 59
59 - DMA2_STREAM3
DMA2_STREAM4 = 60
60 - DMA2_STREAM4
DFSDM1_FLT0 = 61
61 - DFSDM1_FLT0
DFSDM1_FLT1 = 62
62 - DFSDM1_FLT1
CAN2_TX = 63
63 - CAN2_TX
CAN2_RX0 = 64
64 - CAN2_RX0
CAN2_RX1 = 65
65 - CAN2_RX1
CAN2_SCE = 66
66 - CAN2_SCE
OTG_FS = 67
67 - OTG_FS
DMA2_STREAM5 = 68
68 - DMA2_STREAM5
DMA2_STREAM6 = 69
69 - DMA2_STREAM6
DMA2_STREAM7 = 70
70 - DMA2_STREAM7
USART6 = 71
71 - USART6
I2C3_EV = 72
72 - I2C3_EV
I2C3_ER = 73
73 - I2C3_ER
RNG = 80
80 - RNG
FPU = 81
81 - FPU
SPI4 = 84
84 - SPI4
SPI5 = 85
85 - SPI5
FMPI2C1_EV = 95
95 - FMPI2C1_EV
FMPI2C1_ER = 96
96 - FMPI2C1_ER