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embassy_stm32::interrupt

Enum Interrupt

pub enum Interrupt {

Show 140 variants    WWDG = 0,
    PVD_AVD = 1,
    TAMP_STAMP = 2,
    RTC_WKUP = 3,
    FLASH = 4,
    RCC = 5,
    EXTI0 = 6,
    EXTI1 = 7,
    EXTI2 = 8,
    EXTI3 = 9,
    EXTI4 = 10,
    DMA1_STREAM0 = 11,
    DMA1_STREAM1 = 12,
    DMA1_STREAM2 = 13,
    DMA1_STREAM3 = 14,
    DMA1_STREAM4 = 15,
    DMA1_STREAM5 = 16,
    DMA1_STREAM6 = 17,
    ADC = 18,
    FDCAN1_IT0 = 19,
    FDCAN2_IT0 = 20,
    FDCAN1_IT1 = 21,
    FDCAN2_IT1 = 22,
    EXTI9_5 = 23,
    TIM1_BRK = 24,
    TIM1_UP = 25,
    TIM1_TRG_COM = 26,
    TIM1_CC = 27,
    TIM2 = 28,
    TIM3 = 29,
    TIM4 = 30,
    I2C1_EV = 31,
    I2C1_ER = 32,
    I2C2_EV = 33,
    I2C2_ER = 34,
    SPI1 = 35,
    SPI2 = 36,
    USART1 = 37,
    USART2 = 38,
    USART3 = 39,
    EXTI15_10 = 40,
    RTC_ALARM = 41,
    TIM8_BRK_TIM12 = 43,
    TIM8_UP_TIM13 = 44,
    TIM8_TRG_COM_TIM14 = 45,
    TIM8_CC = 46,
    DMA1_STREAM7 = 47,
    FMC = 48,
    SDMMC1 = 49,
    TIM5 = 50,
    SPI3 = 51,
    UART4 = 52,
    UART5 = 53,
    TIM6_DAC = 54,
    TIM7 = 55,
    DMA2_STREAM0 = 56,
    DMA2_STREAM1 = 57,
    DMA2_STREAM2 = 58,
    DMA2_STREAM3 = 59,
    DMA2_STREAM4 = 60,
    ETH = 61,
    ETH_WKUP = 62,
    FDCAN_CAL = 63,
    DMA2_STREAM5 = 68,
    DMA2_STREAM6 = 69,
    DMA2_STREAM7 = 70,
    USART6 = 71,
    I2C3_EV = 72,
    I2C3_ER = 73,
    OTG_HS_EP1_OUT = 74,
    OTG_HS_EP1_IN = 75,
    OTG_HS_WKUP = 76,
    OTG_HS = 77,
    DCMI_PSSI = 78,
    CRYP = 79,
    HASH_RNG = 80,
    FPU = 81,
    UART7 = 82,
    UART8 = 83,
    SPI4 = 84,
    SPI5 = 85,
    SPI6 = 86,
    SAI1 = 87,
    LTDC = 88,
    LTDC_ER = 89,
    DMA2D = 90,
    OCTOSPI1 = 92,
    LPTIM1 = 93,
    CEC = 94,
    I2C4_EV = 95,
    I2C4_ER = 96,
    SPDIF_RX = 97,
    DMAMUX1_OVR = 102,
    DFSDM1_FLT0 = 110,
    DFSDM1_FLT1 = 111,
    DFSDM1_FLT2 = 112,
    DFSDM1_FLT3 = 113,
    SWPMI1 = 115,
    TIM15 = 116,
    TIM16 = 117,
    TIM17 = 118,
    MDIOS_WKUP = 119,
    MDIOS = 120,
    MDMA = 122,
    SDMMC2 = 124,
    HSEM1 = 125,
    ADC3 = 127,
    DMAMUX2_OVR = 128,
    BDMA_CHANNEL0 = 129,
    BDMA_CHANNEL1 = 130,
    BDMA_CHANNEL2 = 131,
    BDMA_CHANNEL3 = 132,
    BDMA_CHANNEL4 = 133,
    BDMA_CHANNEL5 = 134,
    BDMA_CHANNEL6 = 135,
    BDMA_CHANNEL7 = 136,
    COMP = 137,
    LPTIM2 = 138,
    LPTIM3 = 139,
    LPTIM4 = 140,
    LPTIM5 = 141,
    LPUART1 = 142,
    CRS = 144,
    ECC = 145,
    SAI4 = 146,
    DTS = 147,
    WAKEUP_PIN = 149,
    OCTOSPI2 = 150,
    OTFDEC1 = 151,
    OTFDEC2 = 152,
    FMAC = 153,
    CORDIC = 154,
    UART9 = 155,
    USART10 = 156,
    I2C5_EV = 157,
    I2C5_ER = 158,
    FDCAN3_IT0 = 159,
    FDCAN3_IT1 = 160,
    TIM23 = 161,
    TIM24 = 162,

}

Variants§

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WWDG = 0

0 - WWDG

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PVD_AVD = 1

1 - PVD_AVD

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TAMP_STAMP = 2

2 - TAMP_STAMP

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RTC_WKUP = 3

3 - RTC_WKUP

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FLASH = 4

4 - FLASH

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RCC = 5

5 - RCC

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EXTI0 = 6

6 - EXTI0

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EXTI1 = 7

7 - EXTI1

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EXTI2 = 8

8 - EXTI2

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EXTI3 = 9

9 - EXTI3

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EXTI4 = 10

10 - EXTI4

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DMA1_STREAM0 = 11

11 - DMA1_STREAM0

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DMA1_STREAM1 = 12

12 - DMA1_STREAM1

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DMA1_STREAM2 = 13

13 - DMA1_STREAM2

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DMA1_STREAM3 = 14

14 - DMA1_STREAM3

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DMA1_STREAM4 = 15

15 - DMA1_STREAM4

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DMA1_STREAM5 = 16

16 - DMA1_STREAM5

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DMA1_STREAM6 = 17

17 - DMA1_STREAM6

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ADC = 18

18 - ADC

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FDCAN1_IT0 = 19

19 - FDCAN1_IT0

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FDCAN2_IT0 = 20

20 - FDCAN2_IT0

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FDCAN1_IT1 = 21

21 - FDCAN1_IT1

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FDCAN2_IT1 = 22

22 - FDCAN2_IT1

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EXTI9_5 = 23

23 - EXTI9_5

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TIM1_BRK = 24

24 - TIM1_BRK

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TIM1_UP = 25

25 - TIM1_UP

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TIM1_TRG_COM = 26

26 - TIM1_TRG_COM

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TIM1_CC = 27

27 - TIM1_CC

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TIM2 = 28

28 - TIM2

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TIM3 = 29

29 - TIM3

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TIM4 = 30

30 - TIM4

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I2C1_EV = 31

31 - I2C1_EV

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I2C1_ER = 32

32 - I2C1_ER

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I2C2_EV = 33

33 - I2C2_EV

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I2C2_ER = 34

34 - I2C2_ER

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SPI1 = 35

35 - SPI1

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SPI2 = 36

36 - SPI2

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USART1 = 37

37 - USART1

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USART2 = 38

38 - USART2

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USART3 = 39

39 - USART3

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EXTI15_10 = 40

40 - EXTI15_10

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RTC_ALARM = 41

41 - RTC_ALARM

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TIM8_BRK_TIM12 = 43

43 - TIM8_BRK_TIM12

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TIM8_UP_TIM13 = 44

44 - TIM8_UP_TIM13

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TIM8_TRG_COM_TIM14 = 45

45 - TIM8_TRG_COM_TIM14

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TIM8_CC = 46

46 - TIM8_CC

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DMA1_STREAM7 = 47

47 - DMA1_STREAM7

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FMC = 48

48 - FMC

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SDMMC1 = 49

49 - SDMMC1

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TIM5 = 50

50 - TIM5

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SPI3 = 51

51 - SPI3

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UART4 = 52

52 - UART4

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UART5 = 53

53 - UART5

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TIM6_DAC = 54

54 - TIM6_DAC

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TIM7 = 55

55 - TIM7

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DMA2_STREAM0 = 56

56 - DMA2_STREAM0

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DMA2_STREAM1 = 57

57 - DMA2_STREAM1

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DMA2_STREAM2 = 58

58 - DMA2_STREAM2

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DMA2_STREAM3 = 59

59 - DMA2_STREAM3

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DMA2_STREAM4 = 60

60 - DMA2_STREAM4

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ETH = 61

61 - ETH

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ETH_WKUP = 62

62 - ETH_WKUP

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FDCAN_CAL = 63

63 - FDCAN_CAL

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DMA2_STREAM5 = 68

68 - DMA2_STREAM5

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DMA2_STREAM6 = 69

69 - DMA2_STREAM6

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DMA2_STREAM7 = 70

70 - DMA2_STREAM7

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USART6 = 71

71 - USART6

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I2C3_EV = 72

72 - I2C3_EV

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I2C3_ER = 73

73 - I2C3_ER

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OTG_HS_EP1_OUT = 74

74 - OTG_HS_EP1_OUT

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OTG_HS_EP1_IN = 75

75 - OTG_HS_EP1_IN

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OTG_HS_WKUP = 76

76 - OTG_HS_WKUP

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OTG_HS = 77

77 - OTG_HS

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DCMI_PSSI = 78

78 - DCMI_PSSI

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CRYP = 79

79 - CRYP

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HASH_RNG = 80

80 - HASH_RNG

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FPU = 81

81 - FPU

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UART7 = 82

82 - UART7

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UART8 = 83

83 - UART8

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SPI4 = 84

84 - SPI4

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SPI5 = 85

85 - SPI5

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SPI6 = 86

86 - SPI6

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SAI1 = 87

87 - SAI1

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LTDC = 88

88 - LTDC

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LTDC_ER = 89

89 - LTDC_ER

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DMA2D = 90

90 - DMA2D

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OCTOSPI1 = 92

92 - OCTOSPI1

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LPTIM1 = 93

93 - LPTIM1

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CEC = 94

94 - CEC

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I2C4_EV = 95

95 - I2C4_EV

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I2C4_ER = 96

96 - I2C4_ER

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SPDIF_RX = 97

97 - SPDIF_RX

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DMAMUX1_OVR = 102

102 - DMAMUX1_OVR

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DFSDM1_FLT0 = 110

110 - DFSDM1_FLT0

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DFSDM1_FLT1 = 111

111 - DFSDM1_FLT1

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DFSDM1_FLT2 = 112

112 - DFSDM1_FLT2

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DFSDM1_FLT3 = 113

113 - DFSDM1_FLT3

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SWPMI1 = 115

115 - SWPMI1

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TIM15 = 116

116 - TIM15

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TIM16 = 117

117 - TIM16

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TIM17 = 118

118 - TIM17

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MDIOS_WKUP = 119

119 - MDIOS_WKUP

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MDIOS = 120

120 - MDIOS

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MDMA = 122

122 - MDMA

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SDMMC2 = 124

124 - SDMMC2

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HSEM1 = 125

125 - HSEM1

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ADC3 = 127

127 - ADC3

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DMAMUX2_OVR = 128

128 - DMAMUX2_OVR

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BDMA_CHANNEL0 = 129

129 - BDMA_CHANNEL0

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BDMA_CHANNEL1 = 130

130 - BDMA_CHANNEL1

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BDMA_CHANNEL2 = 131

131 - BDMA_CHANNEL2

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BDMA_CHANNEL3 = 132

132 - BDMA_CHANNEL3

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BDMA_CHANNEL4 = 133

133 - BDMA_CHANNEL4

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BDMA_CHANNEL5 = 134

134 - BDMA_CHANNEL5

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BDMA_CHANNEL6 = 135

135 - BDMA_CHANNEL6

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BDMA_CHANNEL7 = 136

136 - BDMA_CHANNEL7

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COMP = 137

137 - COMP

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LPTIM2 = 138

138 - LPTIM2

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LPTIM3 = 139

139 - LPTIM3

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LPTIM4 = 140

140 - LPTIM4

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LPTIM5 = 141

141 - LPTIM5

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LPUART1 = 142

142 - LPUART1

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CRS = 144

144 - CRS

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ECC = 145

145 - ECC

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SAI4 = 146

146 - SAI4

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DTS = 147

147 - DTS

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WAKEUP_PIN = 149

149 - WAKEUP_PIN

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OCTOSPI2 = 150

150 - OCTOSPI2

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OTFDEC1 = 151

151 - OTFDEC1

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OTFDEC2 = 152

152 - OTFDEC2

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FMAC = 153

153 - FMAC

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CORDIC = 154

154 - CORDIC

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UART9 = 155

155 - UART9

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USART10 = 156

156 - USART10

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I2C5_EV = 157

157 - I2C5_EV

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I2C5_ER = 158

158 - I2C5_ER

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FDCAN3_IT0 = 159

159 - FDCAN3_IT0

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FDCAN3_IT1 = 160

160 - FDCAN3_IT1

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TIM23 = 161

161 - TIM23

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TIM24 = 162

162 - TIM24

Trait Implementations§

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impl Clone for Interrupt

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fn clone(&self) -> Interrupt

Returns a copy of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for Interrupt

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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more
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impl InterruptNumber for Interrupt

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fn number(self) -> u16

Return the interrupt number associated with this variant. Read more
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impl PartialEq for Interrupt

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fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl Copy for Interrupt

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impl Eq for Interrupt

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impl StructuralPartialEq for Interrupt

Auto Trait Implementations§

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dst: *mut T)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T> InterruptExt for T
where T: InterruptNumber + Copy,

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unsafe fn enable(self)

Enable the interrupt.
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fn disable(self)

Disable the interrupt.
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fn is_active(self) -> bool

Check if interrupt is being handled.
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fn is_enabled(self) -> bool

Check if interrupt is enabled.
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fn is_pending(self) -> bool

Check if interrupt is pending.
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fn pend(self)

Set interrupt pending.
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fn unpend(self)

Unset interrupt pending.
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fn get_priority(self) -> Priority

Get the priority of the interrupt.
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fn set_priority(self, prio: Priority)

Set the interrupt priority.
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fn set_priority_with_cs(self, _cs: CriticalSection<'_>, prio: Priority)

Set the interrupt priority with an already-acquired critical section Read more
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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.