Struct FilterRegular 

pub struct FilterRegular<'a, 'd, 't, T, M, D>
where
    T: Instance + FilterInterrupt<M>,
    M: FilterMarker + InstanceEvents<T>,
    D: DmaMode,
{ /* private fields */ }

Regular-conversion half of a filter.

Implementations

impl<'a, 'd, 't, T, M> FilterRegular<'a, 'd, 't, T, M, RegDma>

where T: Instance + FilterInterrupt<M>, M: FilterMarker + InstanceEvents<T>,

pub fn ring_buffered<'e, D: Dma<T, M>>( &'e mut self, dma: Peri<'e, D>, irq: impl Binding<D::Interrupt, InterruptHandler<D>> + 'e, dma_buf: &'e mut [u32], ) -> RingBufferedFilter<'e, T, M, RegDma>

Attach a DMA ring buffer to this filter’s regular-conversion data register.

impl<'a, 'd, 't, T, M, D> FilterRegular<'a, 'd, 't, T, M, D>

where T: Instance + FilterInterrupt<M>, M: FilterMarker + InstanceEvents<T>, D: DmaMode,

pub fn assign_transceiver( &mut self, transceiver: &'t dyn TransceiverTrait<T, Enabled>, )

Reassigns the transceiver for regular conversions in-place.

The new transceiver must live at least as long as the previous one ('t), since this does not change the Filter’s lifetime parameter. Use Filter::replace_regular_transceiver if you need to assign a transceiver with a shorter/different lifetime and get the old one back for further mutation.

Note

The regular channel select is shadowed: it takes effect only at the next start_conversion (RSWSTART), so an in-progress conversion keeps using the previously selected channel.

pub fn start_conversion(&mut self)

Start a regular conversion.

Note

The request is ignored while a regular conversion is in progress (RCIP). An injected conversion preempts a running regular conversion, which is restarted and flagged via ResultRegular::pending.

pub async fn read(&mut self) -> Result<ResultRegular, Error>

Await the next regular conversion result.

Does not start a conversion: the conversion must already be running, started by an external trigger, or started via start_and_read. Resolves with the next ResultRegular once a conversion completes.

Note

A starved filter hangs forever: if the assigned transceiver produces no data (no modulator, dead clock, stalled source, or no trigger), no conversion completes and this future stays pending indefinitely. Detect starvation in layers:

• the transceiver is borrowed for the filter’s lifetime, so the source cannot be dropped from under you (type system);
• ClockAbsenceDetector flags a missing or failed source clock;
• Error::Overrun is returned when data is arriving, faster than it is read.

pub async fn start_and_read(&mut self) -> Result<ResultRegular, Error>

Start a regular conversion and await its result.

Equivalent to start_conversion followed by read: the read future waits for the conversion it just launched.

pub fn try_get_result(&mut self) -> Result<ResultRegular, Error>

Attempts to read the current regular conversion result.

Returns ResultRegular if REOCF is set, Error::Overrun if an overrun occurred, or Error::NotReady if no conversion result is available.

The conversion result is sign-extended from 24 to 32 bits and is not scaled.

ResultRegular::pending is set if the regular conversion was delayed by an injected conversion.

Reading the result clears the corresponding data register.

pub fn get_result_unchecked(&mut self) -> ResultRegular

Reads and clears the current regular conversion result without checking REOCF.

The conversion result is sign-extended from 24 to 32 bits and is not scaled.

ResultRegular::pending is set if the regular conversion was delayed by an injected conversion.

The returned data is only valid if REOCF was set before reading.

Note

This path does not check or clear the overrun flag; use try_get_result to propagate overruns.

pub fn end_of_conversion(&self) -> bool

Returns whether a regular conversion result is available.

pub fn overrun(&self) -> bool

Whether the regular overrun flag is set.

pub fn clear_overrun(&self)

Clear the regular overrun flag.

pub fn conversion_in_progress(&self) -> bool

Returns whether a regular conversion is currently in progress or pending.

pub fn set_continuous(&mut self, enabled: bool)

Enables or disables continuous conversion mode.

When enabled, the regular transceiver is converted repeatedly after each conversion request. Disabling it while a continuous conversion is in progress stops the conversion immediately.

Note

Writing CR1 while continuous mode is enabled (RCONT=1) mid-conversion restarts the conversion.

impl<'a, 'd, 't, T, M> FilterRegular<'a, 'd, 't, T, M, RegDma>

where T: Instance + FilterInterrupt<M>, M: FilterMarker + InstanceEvents<T>,

pub fn data_register(&mut self) -> *mut u32

Pointer to RDATAR, for custom DMA setups instead of ring_buffered.

Reading clears the register, hence &mut self. Valid as long as the underlying DfsdmCommon stays enabled; no Rust lifetime ties to it.

Trait Implementations

impl<'a, 'd, 't, T, M> FilterDma<T, M> for FilterRegular<'a, 'd, 't, T, M, RegDma>

where T: Instance + FilterInterrupt<M>, M: FilterMarker + InstanceEvents<T>,

fn data_register(&mut self) -> *mut u32

Pointer to the filter’s data register (RDATAR for the regular half, JDATAR for injected), for custom DMA.

fn start_conversion(&mut self)

Starts a conversion (regular or injected, depending on the half).

fn get_and_clear_overrun(&mut self) -> bool

Checks and clears the overrun flag; returns whether it was set.